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CAT6219-250TD-GT3 参数 Datasheet PDF下载

CAT6219-250TD-GT3图片预览
型号: CAT6219-250TD-GT3
PDF下载: 下载PDF文件 查看货源
内容描述: 500毫安CMOS LDO稳压器 [500mA CMOS LDO Regulator]
分类和应用: 线性稳压器IC调节器电源电路光电二极管输出元件
文件页数/大小: 10 页 / 276 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT6219
PIN DESCRIPTIONS
Pin # Name Function
1
VIN Supply voltage input.
2
GND Ground reference.
Enable input (active high); a 2.5MΩ
3
EN
pull-down resistor is provided.
Optional bypass capacitor connection for
4
BYP
noise reduction and PSRR enhancing.
Adjustable input. Feedback pin
4
ADJ
connected to resistor divider.
5 VOUT LDO Output Voltage.
V
IN
2.3V
to 5.5V
OFF ON
C
IN
1µF
VIN
VOUT
C
OUT
2.2µF
R
1
V
OUT
CAT6219
EN
GND
ADJ
R
2
V
OUT
= 1.24V 1 +
(
R
1
R
2
)
Figure 1. Adjustable Output LDO
PIN FUNCTION
VIN
is the supply pin for the LDO. A small 1μF
ceramic bypass capacitor is required between the V
IN
pin and ground near the device. When using longer
connections to the power supply, C
IN
value can be
increased without limit. The operating input voltage
range is from 2.3V to 5.5V.
EN
is the enable control logic (active high) for the regulator
output. It has a 2.5MΩ pull-down resistor, which
assures that if EN pin is left open, the circuit is disabled.
VOUT
is the LDO regulator output. A small 2.2μF
ceramic bypass capacitor is required between the
VOUT pin and ground. For better transient response,
its value can be increased to 4.7μF.
The capacitor should be located near the device. For
the SOT23-5 package, a continuous 500mA output
current may turn-on the thermal protection. A 250Ω
internal shutdown switch discharges the output
capacitor in the no-load condition.
GND
is the ground reference for the LDO. The pin
must be connected to the ground plane on the PCB.
BYP
is the reference bypass pin. An optional 0.01μF
capacitor can be connected between BYP pin and
GND to reduce the output noise and enhance the
PSRR at high frequency.
ADJ
is the adjustable input pin for the adjustable
LDO. The pin is connected to the resistor voltage
divider.
ABSOLUTE MAXIMUM RATINGS
Parameter
V
IN
V
EN
, V
OUT
Junction Temperature, T
J
Power Dissipation, P
D
Storage Temperature Range, T
S
Lead Temperature (soldering, 5 sec.)
ESD Rating (Human Body Model)
Rating
0 to 6.5
-0.3 to V
IN
+0.3
+150
Internally Limited
(2)
-65 to +150
260
3
Unit
V
V
°C
mW
°C
°C
kV
RECOMMENDED OPERATING CONDITIONS
(3)
Parameter
V
IN
V
EN
Junction Temperature Range, T
J
Package Thermal Resistance (SOT23-5),
θ
JA
Range
2.3 to 5.5
0 to V
IN
-40 to +125
235
Unit
V
V
°C
°C/W
Typical application circuit with external components is shown on page 1.
Notes:
(1) Exceeding maximum rating may damage the device.
(2) The maximum allowable power dissipation at any T
A
(ambient temperature) is P
Dmax
= (T
Jmax
– T
A
) /
θ
JA
. Exceeding the maximum
allowable power dissipation will result in excessive die temperature, and the regulator will go into thermal shutdown.
(3) The device is not guaranteed to work outside its operating rating.
Doc. No. MD-10009 Rev. D
2
©
Catalyst Semiconductor, Inc.
Characteristics subject to change without notice