CAT93C56/57
POWER-UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The CAT93C56/57 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 10-bit instructions for 93C57; seven 11-bit
instructions for 93C56 control the reading, writing and
erase operations of the device. When organized as X8,
seven 11-bit instructions for 93C57; seven 12-bit in-
structions for 93C56 control the reading, writing and
erase operations of the device. The CAT93C56/57
operates on a single power supply and will generate
on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high)
and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high indi-
cates that the device is ready for the next instruction. If
necessary, the DO pin may be placed back into a high
impedance state during chip select by shifting a dummy
“1” into the DI pin. The DO pin will enter the high
impedance state on the falling edge of the clock (SK).
Placing the DO pin into the high impedance state is
recommended in applications where the DI pin and the
4
DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 7-bit address
(93C57)/ 8-bit address (93C56) (an additional bit when
organized X8) and for write operations a 16-bit data field
(8-bit for X8 organizations).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C56/
57 will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (t
PD0
or t
PD1
).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
CSMIN
. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Doc. No. 1088, Rev. M
CATALYST [ CATALYST SEMICONDUCTOR ]
