CM6800
L
OW
S
TART-
U
P
C
URRENT
PFC/PWM C
ONTROLLER
C
OMBO
16
VEAO
IEAO
1
13
VCC
PFC OVP
VCC
17.9V
0.5V
+
-
VCC OVP
2.75V
-
+
.
-
7.5V
REFERENCE
VREF
14
18
VFB
-
GMv
.
2.5V
2
4
ISENSE
IAC
VRMS
+
+
.
-
PFC CMP
+
-
GAIN
MODULATOR
3.5K
3
7
RAMP1
OSCILLATOR
Figure 1. PFC Section Block Diagram
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the types
of compensation networks most commonly used for the
voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V
REF
to produce a soft-start characteristic on the
PFC: as the reference voltage comes up from zero volts, it
creates a differentiated voltage on I
EAO
which prevents the
PFC from immediately demanding a full duty cycle on its
boost converter.
PFC Voltage Loop
There are two major concerns when compensating the
voltage loop error amplifier, V
EAO
; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest anticipated
international power frequency). The gain vs. input voltage
of the CM6800’s voltage error amplifier, V
EAO
has a
specially shaped non-linearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbation in line or
load conditions will cause the input to the voltage error
amplifier (V
FB
) to deviate from its 2.5V (nominal) value. If
this happens, the transconductance of the voltage error
amplifier will increase significantly, as shown in the Typical
Performance
Characteristics.
This
raises
the
gain-bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristics.
2008/10/23
Rev. 2.1
Champion Microelectronic Corporation
+
+
0.3V
-
LOW POWER
DETECT
3.5K
GMi
TRI-FAULT
S
Q
POWER
FACTOR
CORRECTOR
MPPFC
R
Q
VCC
PFC OUT
-1V
+
-
S
Q
12
PFC ILIMIT
R
Q
MNPFC
GND
CLK
The Voltage Loop Gain (S)
=
Δ
V
OUT
Δ
V
FB
Δ
V
EAO
*
*
Δ
V
EAO
Δ
V
OUT
Δ
V
FB
P
IN
* 2.5V
≈
* GM
V
* Z
CV
V
OUTDC 2
*
Δ
V
EAO
* S * C
DC
Z
CV
: Compensation Net Work for the Voltage Loop
GM
v
: Transconductance of VEAO
P
IN
: Average PFC Input Power
V
OUTDC
: PFC Boost Output Voltage; typical designed value is
380V.
C
DC
: PFC Boost Output Capacitor
PFC Current Loop
The current amplifier, I
EAO
compensation is similar to that of
the voltage error amplifier, V
EAO
with exception of the choice
of crossover frequency. The crossover frequency of the
current amplifier should be at least 10 times that of the
voltage amplifier, to prevent interaction with the voltage loop.
It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.
The Current Loop Gain (S)
=
Δ
V
ISENSE
Δ
D
OFF
Δ
I
EAO
*
*
Δ
D
OFF
Δ
I
EAO
Δ
I
SENSE
V
OUTDC
*
R
S
≈
*
GM
I
*
Z
CI
S
*
L
* 2.5
V
Page 10
CHAMP [ CHAMPION MICROELECTRONIC CORP. ]
