CM6903/4
Low Pin Count PFC/PWM C
ONTROLLER
C
OMBO
One of the advantages of this control technique is that it
required only one system clock. Switch 1(SW1) turns OFF
and switch 2 (SW2) turns ON at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With such
synchronized switching, the ripple voltage of the first stage
is reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method,
substantially reducing dissipation in the high-voltage PFC
capacitor.
Z
CV
: Compensation Net Work for the Voltage Loop
GM
v
: Transconductance of VEAO
P
IN
: Average PFC Input Power
V
OUTDC
: PFC Boost Output Voltage; typical designed value is
380V.
C
DC
: PFC Boost Output Capacitor
∆V
EAO
: This is the necessary change of the VEAO to deliver
the designed average input power. The average value is
6V-3V=3V since when the input line voltage increases, the
delta VEAO will be reduced to deliver the same to the output.
To over compensate, we choose the delta VEAO is 3V.
Internal Voltage Ramp
The internal ramp current source is programmed by way of
VEAO pin voltage. When VEAO increases the ramp current
source is also increase. This current source is used to
develop the internal ramp by charging the internal 30pF +12/
-10% capacitor. The frequency of the internal programming
ramp is set internally to 67kHz.
Design PFC ISENSE Filtering
ISENSE Filter, the RC filter between Rs and ISENSE:
There are 2 purposes to add a filter at ISENSE pin:
1.) Protection: During start up or inrush current
conditions, it will have a large voltage cross Rs,
which is the sensing resistor of the PFC boost
converter. It requires the ISENSE Filter to attenuate
the energy.
2.) Reduce L, the Boost Inductor: The ISENSE Filter
also can reduce the Boost Inductor value since the
ISENSE Filter behaves like an integrator before
going ISENSE which is the input of the current error
amplifier, IEAO.
Typical Applications
PFC Section:
PFC Voltage Loop Error Amp, VEAO
The ML4803 utilizes an one pin voltage error amplifier in
the PFC section (VEAO). In the CM6903/4, it is using the
slew rate enhanced transconductance amplifier, which is
the same as error amplifier in the CM6800. The unique
transconductance profile can speed up the conventional
transient response by 10 times. The internal reference of
the VEAO is 2.5V. The input of the VEAO is VFB pin.
PFC Voltage Loop Compensation
The voltage-loop bandwidth must be set to less than 120Hz
to limit the amount of line current harmonic distortion. A
typical crossover frequency is 30Hz.
The Voltage Loop Gain (S)
∆
V
OUT
∆
V
FB
∆
V
EAO
*
*
∆
V
EAO
∆
V
OUT
∆
V
FB
P
IN
* 2.5V
≈
* GM
V
* Z
CV
V
OUTDC 2
*
∆
V
EAO
* S * C
DC
=
2002/12/16
Preliminary
Rev. 0.4
Champion Microelectronic Corporation
Page 9
CHAMP [ CHAMPION MICROELECTRONIC CORP. ]
