CS5101
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
14L PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16L SO Wide
1
2
3
6
7
8
9
10
11
12, 13
14
15
16
5
4
SYNC
V
CC
V
REF
LGnd
V
FB
COMP
RAMP
IS+
IS-
IS COMP
PGnd
V
G
V
C
V
D
AGnd
DGnd
Synchronization input.
Logic supply (10V to 45V).
5.0V voltage reference.
Logic level ground (Analog and digital ground tied).
Error amplifier inverting input.
Error amplifier output and compensation.
RAMP programmable with the external capacitor.
Current sense amplifier non-inverting input.
Current sense amplifier inverting input.
Current sense amplifier compensation and output.
Power ground.
External power switch gate drive.
Output power stage supply voltage (8V to 75V).
External FET DRAIN Voltage Monitor.
Analog Ground.
Digital Ground.
Circuit Description
Block Diagram
V
CC
V
CC
V
REF
REF
5V
OK
+
UVL+
Ð
+
LGnd
Ð
8V/7V
+
SLEEP
Ð
+
0.7V
Ð
Q
1
V
D
V
C
V
G
Q
2
PGnd
IS COMP
V
CC
5V
24.6k
5V
IS
V
FB
+
Ð
COMP
2V
+
5V
Ð
2.4V
Q
I = 200mA
RAMP
5V
+
RAMP
Ð
+
Ð
SYNC
1.65V
5V
+
SYNC
Ð
+
Ð
2.5V
+
Ð
LATCH
Q
1.5V
5V
Q
4
G
1
+
REF_OK
Ð
0.7V
R
Ð
V
CC
_OK
+
S
5V
+
Ð
Ð
+
+
EA
10k
10k
Ð
BUF
+
V
C
Ð
Ð
+ PWM
+
5V
Q
3
Ð
IS-
IS+
+
Ð
4.5V/4.4V
V
CC
G
2
4
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
