CS8140/1
Circuit Description: continued
As long as ENABLE is high or ENABLE is low and the
Watchdog signal is normal, V
OUT
will be at 5V (typ). If
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and
the IC goes into SLEEP mode. Only the ENABLE circuitry
in the IC remains powered up, drawing a quiescent cur-
rent of 250µA.
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
RESET lead (Figure 3) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
The lower and upper window threshold limits of the
watchdog function are set by the value of C
DELAY
. The lim-
its are determined according to the following equations for
the CS8140:
(a)
(b)
t
WDILOWER
= (1.3 x 10
5
)C
DELAY
or
f
WDI(LOWER)
= (7.69 x 10
-6
)C
DELAY-1
t
WDI(UPPER)
= (3.82 x 10
-4
)C
DELAY
or
f
WDI(UPPER)
= (2.62 x 10
-5
)C
DELAY-1
For the CS8141 the lower limit is determined by the equa-
tions in (a) above.
The capacitor C
DELAY
also determines the frequency of the
RESET signal and the POWER-ON- RESET (POR) delay
period.
RESET Function
The RESET function is activated when the Watchdog sig-
nal is outside of its preset window (Figure 3), when the
regulator is in its power up state (Figure 4a) or when V
OUT
drops below V
OUT
-4.5% for more than 2µs (Figure 4b.)
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
train is generated at the RESET lead (Figure 3) until the
correct Watchdog input signal reappears at the lead. The
duration of the RESET pulse is determined by C
DELAY
according to the following equation:
t
WDI(RESET)
= (1
x10
4
)C
DELAY
t
POR
RESET
5V
RESET Circuit Waveforms with Delays Indicated
V
OUT
V
R
HI
V
R
LO
RESET
V
R
LO
V
R
PEAK
t
POR
4a: Power RESET and Power Down
V
OUT
V
OUT
-4.5%
<2mS
³2ms
4b: Undervoltage Triggered RESET
If an undervoltage condition exists, the voltage on the
RESET lead goes low and the delay capacitor, C
DELAY
, is
discharged. RESET remains low until output is in regula-
tion, the voltage on C
DELAY
exceeds the upper switching
threshold and the Watchdog input signal is within its set
window limits (Figure 4). The delay after the output is in
regulation is:
t
POR(typ)
= (4.75 x 10
5
) C
DELAY
The RESET delay circuit is also programmed with the
external cap C
DELAY
.
The output of the reset circuit is an open collector NPN.
RESET is operational down to V
OUT
= 1V. Both RESET and
its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
Application Notes
CS8140 Design Example
Assume that the reset delay must be 200ms minimum.
From the CS8140 data sheet the reset delay has a ±37% tol-
erance due to the regulator.
Assume the capacitor tolerance is ±10%.
t
POR
(min) = (4.75 x 10
5
x 0.63) x C
DELAY
x 0.9
C
DELAY
(min) =
t
POR
(min)
2.69 x 10
5
The CS8140 with its unique integration of linear regulator
and control features: RESET , ENABLE and WATCHDOG,
provides a single IC solution for a microprocessor power
supply. The reset delay, reset duration and watchdog fre-
quency limits are all determined by a single capacitor. For
a particular microprocessor the overriding requirement is
usually the reset delay (also known as power on reset).
The capacitor is chosen to meet this requirement and the
reset duration and watchdog frequency follow.
The reset delay is given by:
t
POR(typ)
= (4.75
x
10
5
)C
DELAY
8
C
DELAY
= (min) = 0.743 µF
Closest standard value is 0.82µF.
Minimum and maximum delays using 0.82µF are 220ms
and 586ms.
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
