CS42526
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(For CQZ, T
A
= -10 to +70° C; For DQZ, T
A
= -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to
5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C
L
= 30 pF)
Parameter
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
Symbol
f
scl
t
irs
t
buf
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
rc
t
fc
t
susp
t
ack
Min
-
500
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.7
-
Max
100
-
-
-
-
-
-
-
-
1
300
-
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Notes:
17. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19.
15 -
15 -
15 -
--------------------
for Single-Speed Mode,
--------------------
for Double-Speed Mode,
-----------------
for Quad-Speed Mode
256
×
Fs
128
×
Fs
64
×
Fs
RST
t
Stop
irs
Start
R e p e a te d
Sta rt
t rd
t fd
Stop
SDA
t
buf
t
hdst
t
high
t
hdst
t fc
t susp
SCL
t
t
t sud
t ack
t sust
t rc
lo w
hdd
Figure 3. Control Port Timing - I²C Format
DS585F1
13
CIRRUS [ CIRRUS LOGIC ]
