CS4329
ANALOG CHARACTERISTICS (CONTINUED)
Parameter
Symbol
(Note 5)
Min
1.90
-
-
4
-
Typ
2.0
2.2
3
-
-
Max
2.10
-
15
-
100
Unit
Vrms
V
mV
kΩ
pf
Analog Output
Differential Full Scale Output Voltage
Output Common Mode Voltage
Differential Offset
AC Load Resistance
Load Capacitance
Notes: 1. Triangular PDF Dithered Data
R
L
C
L
2. AUTO-MUTE active. See parameter definitions
3. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz,
the passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.
4. Group Delay for Fs=48 kHz 25/48 kHz=520
µs
5. Specified for a fully differential output ±((AOUT+)-(AOUT-)). See Figure 12.
SWITCHING CHARACTERISTICS
to 4.75 Volts; C
L
= 20 pF)
Parameter
Input Sample Rate
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
External SCLK Mode
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
(T
A
= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = VA = 5.25
Symbol
Fs
Min
1
10
10
21
21
31
32
20
20
1 -
-------------------
128
(
Fs
)
MCLK / LRCK = 512
MCLK / LRCK = 512
MCLK / LRCK = 384
MCLK / LRCK = 384
MCLK / LRCK = 256
MCLK / LRCK = 256
t
sclkl
t
sclkh
t
sclkw
t
slrd
t
slrs
t
sdlrs
t
sdh
t
sclkw
t
sdlrs
t
sdh
t
sdh
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
SCLK Period
SCLK / LRCK = 64
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
SCLK rising to SDATA hold time
MCLK / LRCK = 256 or 512
MCLK / LRCK = 384
20
20
20
20
1 -
----------------
64
(
Fs
)
1 -
------------------- + 10
512
(
Fs
)
1 -
------------------- + 15
512
(
Fs
)
1 -
------------------- + 15
384
(
Fs
)
DS153F1
3
CIRRUS [ CIRRUS LOGIC ]
