CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2
C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, C
L
= 20 pF)
Parameter
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
(Note 7)
Symbol
f
scl
t
irs
t
buf
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
rc
, t
rc
t
fc
, t
fc
t
susp
t
ack
Min
-
500
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.7
300
Max
100
-
-
-
-
-
-
-
-
1
300
-
1000
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Notes: 7. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
RST
t
S to p
irs
S t a rt
R e p e a te d
S t a rt
t rd
t fd
S to p
SDA
t
buf
t
h d st
t
h igh
t
h d st
t fc
t su sp
SCL
t
t
t sud
t a ck
t sust
t rc
lo w
hdd
Figure 2. Control Port Timing - I
2
C Format
12
DS566PP2
CIRRUS [ CIRRUS LOGIC ]
