CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, C
L
= 20 pF)
Parameter
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 9)
(Note 10)
(Note 10)
(Note 8)
Symbol
f
sclk
t
srs
t
spi
t
csh
t
css
t
scl
t
sch
t
dsu
t
dh
t
r2
t
f2
Min
-
500
500
1.0
20
66
66
40
15
-
-
Max
6
-
-
-
-
-
-
-
-
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes: 8. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F
SCK
< 1 MHz.
RST
t srs
CS
t spi t css
CCLK
t r2
C D IN
t scl
t
sch
t
csh
t f2
t dsu t
dh
Figure 3. Control Port Timing - SPI Format (Write)
DS566PP2
13
CIRRUS [ CIRRUS LOGIC ]
