CS4922
SWITCHING CHARACTERISTICS - CONTROL PORT (I
2
C MODE)
VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, C
L
= 20pF)
Parameter
Symbol
Min
Max
100
400
4.7
4.0
4.7
1.2
4.0
1.0
250
0
50
300
40
40
200
0
50
20
4.7
Units
kHz
µs
µs
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
(T
A
= 25
°C;
I
2
C
®
Mode (CS=1)
SCK/SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
SDA Setup Time to SCK/SCL Rising
SDA Hold Time from SCK/SCL Falling
Rise Time of Both SDA and SCK/SCL
Fall Time of Both SDA and SCK/SCL
Time from SCK/SCL Falling to CS4920 ACK
Time from SCK/SCL Falling to SDA
Valid During READ Operation
Time from SCK/SCL Rising to REQ Rising
Hold Time for REQ from SCK/SCL Rising
Rise Time for REQ
Fall Time for REQ
Setup Time for Stop Condition
slow
fast
slow
fast
(slow mode)
(fast mode)
(Note 10)
f
scl
t
buf
t
hdst
t
low
t
high
t
sud
(Note 11)
(Note 12)
t
hdd
t
r
t
f
t
sca
t
scsdv
(Note 13)
(Note 14)
(Note 13)
(Note 14)
t
scrh
t
scrl
t
rr
t
rf
t
susp
Notes: 10. Use of I
2
C
®
bus compatible interface requires a license from Philips.
11. Data must be held for sufficient time to bridge the 300ns transition time of SCK/SCL.
12. This rise time is shorter than the I
2
C specifications recommend, please refer to the section on SCP
communications for more information.
13. REQ will only go HIGH if there is no data in the SCPOUT register at the rising edge of SCL/SCK during
a READ operation as shown. DSP frequency is 20 MHz. Pull-up resistor is 2 kΩ C
L
= 20pF.
14. if REQ went HIGH as indicated in Note 13 then REQ will hold HIGH at least until the next rising edge of
SCK/SCL. If data is in the SCPOUT register at this time REQ will go active LOW again. This condition
should be treated as a new READ process. The address and R/W should be sent again following a new
START condition.
10
CIRRUS [ CIRRUS LOGIC ]
