CS4922
SWITCHING CHARACTERISTICS - CONTROL PORT (SPI MODE)
VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, C
L
= 20pF)
Parameter
Symbol
(slow mode)
(fast mode)
(slow mode)
(slow mode)
(slow mode)
(fast mode)
(slow mode)
(fast mode)
(slow mode)
(fast mode)
(slow mode)
(fast mode)
(Note 6)
(Note 7)
(Note 7)
(Note 8)
(Note 9)
(Note 9)
f
sck
f
sck
t
css
t
r
t
f
t
f
t
scl
t
scl
t
sch
t
sch
t
cdisu
t
cdih
t
scdov
t
scrh
t
rr
t
rf
t
scrl
t
sccsh
t
csht
Min
-
-
20
-
-
-
1100
150
1100
150
250
50
50
-
-
-
-
0
20
200
Max
350
2000
-
50
300
50
-
-
-
-
-
-
-
40
200
50
20
-
-
-
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(T
A
= 25
°C;
SPI Mode (CS = 0)
SCK/SCL Clock Frequency
CS Falling to SCK/SCL Rising
Rise Time of Both CDIN and SCK/SCL Lines
Fall Time of Both CDIN and SCK/SCL Lines
SCK/SCL Low Time
SCK/SCL High Time
Setup Time CDIN to SCK/SCL Rising
Hold Time SCK/SCL Rising to CDIN
Transition Time from SCK/SCL to CDOUT Valid
Time from SCK/SCL Rising to REQ Rising
Rise Time for REQ
Fall Time for REQ
Hold Time for REQ from SCK/SCL Rising
Time from SCK/SCL Falling to CS Rising
High Time Between Active CS
Notes: 6. Data must be held for sufficient time to bridge 300(50) ns transition time of SCK/SCL.
7. CDOUT should NOT be sampled during this time period.
8. REQ will only go HIGH if there is no data in SCPOUT at the rising edge of SCL/SCK during a READ
operation as shown. DSP frequency is 20 MHz. Pull-up resistor is 2 kΩ. C
L
= 20 pF.
9. If REQ went HIGH as indicated in note 7, then REQ will hold high at least until the next rising edge of
SCK/SCL. If data is in SCPOUT at this time REQ will go active LOW again. This condition should be
treated as a new READ process. Address and R/W bit should be sent again.
8
CIRRUS [ CIRRUS LOGIC ]
