CS5101A CS5102A
SWITCHING CHARACTERISTICS
(Continued)
Parameter
Symbol
t
sclk
t
sclkl
t
sclkh
t
dss
PDT Mode
(Note 30)
t
dhs
t
dts
t
slkl
t
slkh
t
ss
t
sh
t
rsclk
CS5101A
CS5102A
CS5101A
CS5102A
t
rsdl
t
rsdl
t
hfs
thfs
Min
200
50
50
-
-
-
-
-
2t
clk
-100
2t
clk
-100
-
-
-
6tclk
6t
clk
-
Typ
-
-
-
100
140
65
2t
clk
2t
clk
-
-
2t
clk
2t
clk
2tclk
Max
-
-
-
150
230
125
-
-
-
-
-
2tclk+165
2t
clk
+200
8t
clk
+165
8t
clk
+200
-
Units
ns
ns
ns
ns
ns
ns
t
clk
t
clk
ns
ns
ns
ns
ns
ns
ns
t
clk
PDT and RBT Modes
SCLK Input Pulse Period
SCLK Input Pulse Width Low
SCLK Input Pulse Width High
SCLK Input Falling to SDATA Valid
HOLD Falling to SDATA Valid
TRK1, TRK2 Falling to SDATA Valid
FRN and SSC Modes
SCLK Output Pulse Width Low
SCLK Output Pulse Width High
SDATA Valid Before Rising SCLK
SDATA Valid After Rising SCLK
SDL Falling to 1st Rising SCLK
Last Rising SCLK to SDL Rising
HOLD Falling to 1st Falling SCLK
CH1/2 Edge to 1st Falling SCLK
-
-
7tclk
t
chfs
Note: 30. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then
SDATA is valid t
dss
time after the next falling SCLK.
DIGITAL CHARACTERISTICS
(T
A
= T
min
to T
max
;
VD- = 5V
±
10%)
Parameter
Calibration Memory Retention
Power Supply Voltage VA+ and VD+
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
Digital Output Pin Capacitance
(Note 32)
IOUT = 1.6 mA
(Note 31)
VA+, VD+ = 5V
±
10%; VA-,
Min
2.0
2.0
-
(VD+)-1.0
-
-
-
Typ
-
-
-
-
-
-
9
Max
-
-
0.8
-
0.4
10
-
Units
V
V
V
V
V
µA
pF
Symbol
V
MR
V
IH
V
IL
V
OH
V
OL
I
in
C
out
Notes: 31. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be
allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+.
This parameter is guaranteed by characterization.
32. I
OUT
= -100
µ
A. This specification guarantees TTL compatibility (V
OH
= 2.4V @ Iout = -40
µ
A).
DS45F2
9
CIRRUS [ CIRRUS LOGIC ]
