CS5317
Data Output Characteristics & Coding Format
manently damaged. If the two supplies are de-
rived from separate sources, care must be taken
that the analog supply comes up first at power-up.
Figure 1 shows a decoupling scheme which al-
lows the CS5317 to be powered from a single set
As shown in Figure 4, the CS5317 outputs its 16-
bit data word in a serial burst. The data appears at
the DATA pin on the rising edge of the same
CLKOUT cycle in which DOUT falls. Data
changes on the rising edge of CLKOUT, and can
be latched on the falling edge. The CLKOUT rate
±
of 5V rails. The digital supplies are derived
from the analog supplies through 10 Ω resistors
to prevent the analog supply from dropping be-
low the digital supply.
is set by the CLKIN input (f
/2 in the CLKOR
clkin
mode; f
*128 in the CLKG1 mode; and
clkin
f
*256 in the CLKG2 mode). DOUT returns
clkin
PLL Characteristics
high after the last bit is transmitted. After trans-
mitting the sixteen data bits, DATA will remain
high until DOUT falls again, initiating the next
data output cycle.
A phase-locked loop is included on the CS5317
and is used to generate the requisite high fre-
quency A/D sampling clock. A functional
diagram of the PLL is shown in Figure 5. The
PLL consists of a phase detector, a filter, a VCO
(voltage-controlled oscillator), and a counter/di-
A 3-state capability is available for bus-oriented
applications. The 3-state control input is termed
Data Output Enable, DOE, and is asynchronous
with respect to the rest of the CS5317. If DOE is
taken high at any time, even during a data burst,
the DATA, DOUT and CLKOUT pins go to a
high impedance state. Any data which would be
output while DOE is high is lost.
vider. The phase detector inputs are CLKIN (θ )
1
and a sub-multiple of the VCO output signal (θ ).
2
The inputs to the phase detector are positive-edge
triggered and therefore the duty cycle of the
CLKIN signal is not significant. With this type of
phase detector, the lock range of the PLL is equal
to the capture range and is independent of the low
pass filter. The output of the phase detector is in-
put to an external low pass filter. The filter
characteristics are used to determine the transient
response of the loop. The output voltage from the
filter functions as the input control voltage to the
VCO. The output of the VCO is then divided in
frequency to provide an input to the phase detec-
tor. The clock divider ratio is a function of the
PLL mode which has been selected.
Power Supplies
Since the A/D converter’s output is digitally fil-
tered in the CS5317, the device is more forgiving
and requires less attention than conventional 16-
bit A/D converters to grounding and layout
arrangements. Still, care must be taken at the de-
sign and layout stages to apply the device
properly. The CS5317 provides separate analog
and digital power supply connections to isolate
digital noise from its analog circuitry. Each sup-
ply pin should be decoupled to its respective
ground, AGND or DGND. Decoupling should be
accomplished with 0.1 µF ceramic capacitors. If
significant low frequency noise is present in the
supplies, 10 µF tantalum capacitors are recom-
mended in parallel with the 0.1 µF capacitors.
Phase Detector Gain (Kd)
A properly designed and operating phase-locked
loop can be described using steady state linear
analysis. Once in frequency lock, any phase dif-
ference between the two inputs to the phase
detector cause a current output from the detector
during the phase error. While either the +50 µA or
the -50 µA current source may be turned on, the
average current flow is:
The positive digital power supply of the CS5317
must never exceed the positive analog supply by
more than a diode drop or the chip could be per-
DS27F4
11
CIRRUS [ CIRRUS LOGIC ]
