CS5317
tio sets the ratio of the VCO frequency to the
CLKIN frequency. As illustrated in Figure 5, the
VCO output is always divided by two to yield the
CLKOUT signal which is identical in frequency
to the delta-sigma modulator sampling clock.
The CLKOUT signal is then further divided by
either 128 in the CLKG1 mode or by 256 in the
CLKG2 mode. When the divide by two stage is
included, the divider ratio (N) for the PLL in the
CLKG1 mode is effectively 256. In the CLKG2
mode the divider ratio (N) is 512.
i
= Kd(θ −θ ) ≈ (−50µA ⁄ 2π) (θ −θ )
1 2 1 2
out
avg
where θ is the phase of IN1, θ is the phase of
1
2
IN2 and Kd is the phase detector gain. The factor
2π comes from averaging the current over a full
CLKIN cycle. Kd is in units of micro-am-
peres/radian.
VCO Gain (Ko)
The output frequency from the VCO ranges from
1.28 MHz to 5.12 MHz. The frequency is a func-
tion of the control voltage input to the VCO. The
VCO has a negative gain factor, meaning that as
the control voltage increases more positively the
output frequency decreases. The gain factor units
are Megaradians per Volt per Second. This is
equivalent to 2π Megahertz per volt. Changes in
output frequency are given by:
Loop Transfer Function
As the phase-locked loop is a closed loop system,
an equation can be determined which describes its
closed loop response. Using the gain factors for
the phase detector and the VCO, the filter ar-
rangement and the counter/divider constant N,
analysis will yield the following equation which
describes the transfer function of the PLL:
∆ω = Ko ∆VCO
[Ko is typ. -10Mrad/Vs.]
vco
in
KoKdR
N
KoKd
NC
s +
Counter/Divider Ratio
θ
θ
2
1
=
KoKdR
KoKd
NC
2
s +
s +
The CS5317 PLL multiplies the CLKIN rate by
an integer value. To set the multiplication rate, a
counter/divider chain is used to divide the VCO
output frequency to develop a clock whose fre-
quency is compared to the CLKIN frequency in
the phase detector. The binary counter/divider ra-
N
This equation may be rewritten such that its ele-
ments
correspond
with
the
following
+5V
VA+
External RC
50 µA
K
=
-8
µ
A/rad
d
C
1
C
2
R
IN1
DOWN
CLKOR
CLKIN
Phase/Frequency
Detect Logic
VCO
2
Delta-Sigma
Sampling Clock
(CLKOUT)
PHDT VCOIN
CLKOR
IN2
UP
K
= -10 Mrad/V.s
0
2
50
-5V
µ
A
CLKG2
CLKG1
128
2
Conversion Output Rate -
Same Frequency as DOUT
Internal Sync for Digital Filter
Figure 5. PLL Functional Diagram
12
DS27F4
CIRRUS [ CIRRUS LOGIC ]
