CS5364
2. TYPICAL CONNECTION DIAGRAM
Resistor may only be used if
VD is derived from VA. If used,
do not drive any other logic
from VD.
+
1
μ
F
+5V to 3.3V
+5V
+
1
μ
F
0.01
μ
F
VA
6
5.1
Ω
4, 9
33
0.01
μF
VD
35
0.01
μF
220
μ
F
+
0.1
μF
FILT+
REF_GND
VQ
GND
VLC
5
7
+5V to 1.8V
1
μ
F
+
0.1
μF
8
Channel 1 Analog
Input Buffer
47
48
1
2
13
14
11
12
AIN 1+
AIN 1-
AIN 2+
AIN 2-
AIN 3+
AIN 3-
AIN 4+
AIN 4-
CS5364
MODE1/SCL/CCLK
MODE0/SDA/CDOUT
OVFL
DIF1/AD1/CDIN
DIF0/AD0/CS
RST
MDIV
CLKMODE
40
36
37
38
41
42
34
Power Down
and Mode
Settings
Channel 2 Analog
Input Buffer
Channel 3 Analog
Input Buffer
A/D CONVERTER
VLS
28
0.01
μF
+5V to 1.8V
Channel 4 Analog
Input Buffer
SDOUT1/TDM
SDOUT2
TDM
RESERVED
LRCK/FS
30
27
31
26
24
25
23
Audio Data
Processor
SCLK
MCLK
Timing Logic
and Clock
VX
XTI
XTO
GND
3, 8,10, 15, 16, 17, 18,
19, 29, 32, 43, 44, 45, 46
20
+5V
21
22
Figure 2. Typical Connection Diagram
For analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low-cost single-ended-to-differen-
tial solution is provided on the Customer Evaluation Board.
DS625F2
9
CIRRUS [ CIRRUS LOGIC ]
