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CS5368-CQZ 参数 Datasheet PDF下载

CS5368-CQZ图片预览
型号: CS5368-CQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 114分贝192千赫, 8通道A / D转换器 [114 dB, 192 kHz, 8-Channel A/D Converter]
分类和应用: 转换器模数转换器PC
文件页数/大小: 41 页 / 712 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5368
Pin Name
AIN2+, AIN2-
AIN4+, AIN4-
AIN3+, AIN3-
AIN7+, AIN7-
AIN8+, AIN8-
AIN6+, AIN6-
AIN5+, AIN5-
AIN1+, AIN1-
GND
VA
REF_GND
FILT+
VQ
VX
XTI
XTO
MCLK
Pin #
1,2
11,12
13,14
15,16
17,18
43,44
45,46
47,48
3,8
10,19
29,32
4,9
5
6
7
20
21
22
23
Pin Description
Differential Analog
(Inputs) - Audio signals are presented differently to the delta sigma modula-
tors via the AIN+/- pins.
Ground
(Input) - Ground reference. Must be connected to analog ground.
Analog Power
(Input) - Positive power supply for the analog section
Reference Ground
(Input) - For the internal sampling circuits. Must be connected to analog
ground.
Positive Voltage Reference
(Output) - Reference voltage for internal sampling circuits.
Quiescent Voltage
(Output) - Filter connection for the internal quiescent reference voltage.
Crystal Oscillator Power
(Input) - Also powers control logic to enable or disable oscillator cir-
cuits.
Crystal Oscillator Connections
(Input/Output) - I/O pins for an external crystal which may be
used to generate MCLK.
System Master Clock
(Input/Output) - When a crystal is used, this pin acts as a buffered MCLK
Source (Output). When the oscillator function is not used, this pin acts as an input for the system
master clock. In this case, the XTI and XTO pins must be tied low.
Serial Audio Channel Clock
(Input/Output)
In I²S Mode, Serial Audio Channel Select. When low, the odd channels are selected.
In LJ Mode, Serial Audio Channel Select. When high, the odd channels are selected.
In TDM Mode, a frame sync signal. When high, it marks the beginning of a new frame of serial
audio samples. In Slave Mode, this pin acts as an input pin.
Main timing clock for the Serial Audio Interface
(Input/Output) - During Master Mode, this pin
acts as an output, and during Slave Mode it acts as an input pin.
Serial Audio Data
(Output) - Channels 7,8.
Serial Audio Data
(Output) - Channels 3,4.
Serial Audio Interface Power
(Input) - Positive power for the serial audio interface.
Serial Audio Data
(Output) - Channels 1,2.
Serial Audio Data
(Output) - Channels 5,6. TDM is complementary TDM data.
Digital Power
(Input) - Positive power supply for the digital section/
Control Port Interface Power(Input)
- Positive power for the control port interface.
Overflow
(Output,
open drain)
- Detects an overflow condition on both left and right channels.
Reset
(Input) - The device enters a low power mode when low.
CLKMODE
(Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the
core device circuitry.
DIF1, DIF0
(Input) - Inputs of the audio interface format.
Mode Selection
(Input) - Determines the operational mode of the device.
MCLK Divider
(Input) - Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the
core device circuitry.
LRCK/FS
24
SCLK
SDOUT4
SDOUT2
VLS
SDOUT1/TDM
SDOUT3/TDM
VD
VLC
OVFL
RST
25
26
27
28
30
31
33
35
36
41
Stand-Alone Mode
CLKMODE
DIF1
DIF0
M1
M0
MDIV
34
37
38
39
40
42
DS624F2
7