CS5396 CS5397
A calibration of the tri-level delta-sigma modulator
should always be initiated following power-up and
after allowing sufficient time for the voltage on the
external VREF capacitor to settle. This is required
to minimize noise and distortion. It is also advised
that the CS5396/97 be calibrated after the device
has reached thermal equilibrium, approximately 10
seconds, to maximize performance.
CONTROL PORT MODE
Access to Control Port Mode
The mode selection between Stand-Alone and Con-
trol Port Mode is determined by the state of the
SDATA1 pin 250 MCLK cycles following the in-
ternal power-on reset. A 47 kΩ pull-up resistor on
SDATA1 will select the Control Port Mode. How-
ever, the control port will not respond to CCLK and
CDIN until the pull-up on the SDATA1 pin is re-
leased.
Synchronization of Multiple Devices -
Stand Alone Mode
In systems where multiple ADCs are required, care
must be taken to achieve simultaneous sampling. It
is recommended that the rising edge of the CAL
signal be timed with a falling edge of MCLK to en-
sure that all devices will initiate a calibration and
synchronization sequence on the same rising edge
of MCLK. The absence of re-timing of the CAL
signal can result in a sampling difference of one
MCLK period.
Internal Power-On Reset
The timing required to determine Control port
2
mode and I S/SPI mode is based on an internal
power-on reset. The internal power-on reset re-
quires the power supply to exceed a threshold volt-
age. However, there is no external indication of
when the internal reset is activated. If precise tim-
2
ing of the Control port and I S/SPI decisions is re-
quired, MCLK should not be applied until the
power supply has stabilized.
LRCK
SCLK
Left
Right
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
MASTER
24-Bit Left Justified Data
Data Valid on Rising Edge of 64x SCLK Data Valid on Rising Edge of SCLK
MCLK equal to 256x Fs MCLK equal to 256x Fs
SLAVE
24-Bit Left Justified Data
Figure 2. Serial Data Format 0, Stand-Alone Mode, DFS low. Left Justified.
LRCK
SCLK
Left
Right
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
MASTER
2
SLAVE
2
I S 24-Bit Data
I S 24-Bit Data
Data Valid on Rising Edge of 64x SCLK
MCLK equal to 256x Fs
Data Valid on Rising Edge of SCLK
MCLK equal to 256x Fs
Figure 3. Serial Data Format 1, Stand-Alone Mode, DFS High. I2S compatible
14
DS229PP2
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