CS5471
centage of full scale. Table 1 below illustrates the
ideal relationship between the differential voltage
presented any one of the input channels and the
corresponding output code. Note that for the cur-
rent channels, the state of the GAIN input pin is as-
sumed to driven low, such that the PGA gain on the
current channels is 1x. If the PGA gain of the cur-
rent channels is set to 20x, then a +40 mV differen-
tial voltage presented across the “IIN+” and “IIN-”
pins will cause a (nominal) output code of 32767.
Input Voltage
(mV
0-pk
)
+800
0.0122 to 0.0366
-0.0122 to 0.0122
-0.0122 to -0.0366
-800
Output Code Output Code
(hexadecimal)
(decimal)
7FFF
0001
0000
FFFF
8000
32767
1
0
-1
-32768
1
–
z
– 256
3
-
H
(
z
)
=
---------------------
–1
1
–
z
If the OWRS pin is set to logic high, then the trans-
fer function is
1
–
z
– 128
3
-
H
(
z
)
=
---------------------
–1
1
–
z
The above filter samples the modulator bit stream
at XIN/8 Hz and decimates to XIN/1024 Hz.
2.4
Table 1. Nominal Relationship for Differential Input
Voltage vs. Output Code, for all channels. (Assume PGA
gain is set to 1x.)
Serial Interface
2.3
High Rate Digital Filters
The CS5471 communicates with a target device via
a master serial data output port. Output data is pro-
vided on the SDO output synchronous with the
SCLK output.
A third output, FSO, is a framing signal used to sig-
nal the start of output data. These three outputs will
be driven as long as the SE (serial enable) input is
held high. Otherwise, these outputs will be high im-
pedance.
If the OWRS pin is set to logic low, the high-rate
filters are implemented as fixed sinc
3
filters with
the following transfer function:
This filter samples the modulator bit stream at
XIN/8 Hz and decimates to XIN/2048 Hz.
SCLK
FSO
Each data segment
is 16 bits long.
SDO
Channel 1 (V)
64 0-value bits
Channel 1 (I)
Figure 3. Serial Port Data Transfer
8
CIRRUS [ CIRRUS LOGIC ]
