CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE
Inputs: Logic 0 = 0 V, Logic 1 = VD+; C
L
= 20 pF.
Parameter
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
f
sck
t
csh
t
css
t
scl
t
sch
t
dsu
t
dh
t
pd
t
r1
t
f1
t
r2
t
f2
Min
0
1.0
20
66
66
40
18
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
6.0
-
-
-
-
-
-
45
25
25
100
100
Units
MHz
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13. If Fso or Fsi is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fso and
less than 128 Fsi. This is dictated by the timing requirements necessary to access the Channel Status and
User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The
minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz
should be safe for all possible conditions.
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For f
sck
< 1 MHz.
CS
t css
CCLK
t r2
CDIN
t dsu
t dh
t f2
t scl
t sch
t csh
t pd
CDOUT
Figure 3. SPI Mode Timing
10
DS245F4
CIRRUS [ CIRRUS LOGIC ]
