EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Pin List
The following Thin-profile Fine-pitch Ball Grid Array (TFBGA) ball assignment table is sorted in order of ball.
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
CSn[1]
CSn[7]
E1
E2
SDCSn[2]
SDWEN
DA[22]
AD[3]
J10
J12
J13
J14
J15
J16
J17
K1
gndc
vddc
P1
P2
SPCLK
P[10]
A3
SDCLKEN
DA[31]
E3
vddr
P3
P[11]
A4
E4
COL[5]
COL[6]
CSn[0]
COL[3]
AD[4]
P4
P[3]
A5
DA[29]
E5
DA[15]
AD[21]
DA[17]
vddr
P5
AD[15]
AD[13]
AD[12]
DA[2]
A6
DA[27]
E6
P6
A7
HGPIO[2]
RDn
E7
P7
A8
E8
P8
A9
MIIRXD[3]
RXDVAL
MIITXD[1]
CRS
E9
vddr
K2
DA[12]
DA[10]
DA[11]
vddr
P9
AD[8]
A10
A11
A12
A13
A14
A15
A16
A17
B1
E10
E11
E12
E13
E14
E15
E16
E17
F1
vddr
K3
P10
P11
P12
P13
P14
P15
P16
P17
R1
TCK
MIIRXD[0]
TXERR
EGPIO[2]
EGPIO[4]
EGPIO[3]
sXp
K4
BOOT[1]
EEDAT
GRLED
RDLED
GGPIO[2]
RXD[1]
RXD[2]
P[9]
K5
FGPIO[7]
FGPIO[0]
WAITn
K6
gndr
K8
gndc
K9
gndc
USBm[2]
ASDI
K10
K12
K13
K14
K15
K16
K17
L1
gndc
sXm
vddc
AD[25]
RASn
COL[4]
PLL_VDD
COL[2]
COL[1]
COL[0]
DA[9]
B2
CSn[2]
F2
SDCSn[1]
SDCSn[0]
DQMn[3]
AD[5]
R2
HSYNC
P[6]
B3
CSn[6]
F3
R3
B4
AD[20]
F4
R4
P[5]
B5
DA[30]
F5
R5
P[0]
B6
AD[18]
F6
gndr
R6
AD[14]
DA[4]
B7
HGPIO[3]
AD[17]
F7
gndr
L2
AD[2]
R7
B8
F8
gndr
L3
AD[1]
R8
DA[1]
B9
RXCLK
MIIRXD[1]
MIITXD[2]
TXEN
F9
vddc
L4
DA[8]
R9
DTRn
B10
B11
B12
B13
B14
B15
B16
B17
C1
F10
F11
F12
F13
F14
F15
F16
F17
G1
G2
G3
G4
G5
G6
G12
G13
vddc
L5
BLANK
gndr
R10
R11
R12
R13
R14
R15
R16
R17
T1
TDI
gndr
L6
BOOT[0]
ASYNC
SSPTX[1]
PWMOUT
USBm[0]
ABITCLK
USBp[0]
NC
EGPIO[7]
EGPIO[5]
ADC_GND
EGPIO[6]
sYm
L12
L13
L14
L15
L16
L17
M1
M2
M3
M4
M5
M6
M7
M8
gndr
FGPIO[5]
EGPIO[15]
USBp[2]
ARSTn
ADC_VDD
AD[23]
ROW[7]
ROW[5]
PLL_GND
XTALI
XTALO
BRIGHT
AD[0]
sYp
DQMn[0]
CASn
C2
DA[26]
T2
NC
C3
CSn[3]
DA[21]
AD[22]
vddr
DQMn[1]
DQMn[2]
P[17]
T3
V_CSYNC
P[7]
C4
DA[25]
T4
C5
AD[24]
T5
P[2]
C6
AD[19]
gndr
gndr
T6
DA[7]
C7
HGPIO[5]
WRn
gndr
gndr
T7
AD[11]
AD[9]
C8
EGPIO[9]
vddc
T8
42
Copyright 2004 Cirrus Logic (All Rights Reserved)
DS667PP3
CIRRUS [ CIRRUS LOGIC ]
