EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Universal Asynchronous
Receiver/Transmitters (UARTs)
Three 16550-compatible UARTs are supplied. Two
provide asynchronous HDLC (High-level Data Link
Control) protocol support for full duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. A third IrDA
®
compatible UART is also supplied.
•
UART1 supports modem bit rates up to 115.2 Kbps,
supports HDLC and includes a 16 byte FIFO for
receive and a 16 byte FIFO for transmit. Interrupts are
generated on Rx, Tx and modem status change.
UART2 contains an IrDA encoder operating at either
the slow (up to 115 Kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16
byte FIFO for receive and a 16 byte FIFO for transmit.
UART3 supports HDLC and includes a 16 byte FIFO
for receive and a 16 byte FIFO for transmit. Interrupts
are generated on Rx and Tx.
Table H. Universal Asynchronous Receiver / Transmitters Pin
Assignments
Triple Port USB Host
The USB Open Host Controller Interface (Open HCI)
provides full speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB “tiered-
start” topology.
This includes the following features:
•
•
•
Compliance with the USB 2.0 specification
Compliance with the Open HCI Rev 1.0 specification
Supports both low speed (1.5 Mbps) and full speed
(12 Mbps) USB device connections
• Root HUB integrated with 3 downstream USB ports
• Transceiver buffers integrated, over-current protection
on ports
• Supports power management
• Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:
•
•
•
•
Fetches endpoint descriptors and transfer descriptors
Accesses endpoint data from system memory
Accesses the HC communication area
Writes status and retire transfer descriptor
Table I. Triple Port USB Host Pin Assignments
•
•
Pin Mnemonic
TXD0
RXD0
CTSn
DSRn/DCDn
DTRn
RTSn
EGPIO[0]/RI
TXD1/SIROUT
RXD1/SIRIN
TXD2
RXD2
TENn
Pin Name - Description
UART1 Transmit
UART1 Receive
UART1 Clear To
Send / Transmit Enable
UART1 Data Set
Ready / Data Carrier Detect
UART1 Data Terminal Ready
UART1 Ready To Send
UART1 Ring Indicator
UART2 Transmit / IrDA
Output
UART2 Receive / IrDA Input
UART3 Transmit
UART3 Receive
HDLC3 Transmit Enable
Pin Mnemonic
USBp[2:0]
USBm[2:0]
Pin Name - Description
USB Positive signals
USB Negative Signals
Two-Wire Interface With EEPROM Support
The two-wire interface provides communication and
control for EEPROM devices.
Table J. Two-Wire Port with EEPROM Support Pin Assignments
Pin Mnemonic
EECLK
EEDATA
Pin Name - Description
EEPROM / Two-Wire
Interface Clock
EEPROM / Two-Wire
Interface Data
Alternative
Usage
General
Purpose I/O
General
Purpose I/O
Internal Boot ROM
The Internal 16 Kbyte ROM allows booting from FLASH
memory, SPI or UART.
©
DS667PP3
Copyright 2004 Cirrus Logic (All Rights Reserved)
9
CIRRUS [ CIRRUS LOGIC ]
