EP9315
Enhanced Universal Platform SOC Processor
Inter-IC Sound - I
2
S
Parameter
SCLK cycle time
SCLK high time
SCLK low time
SCLK rise/fall time
SCLK to LRCLK assert delay time
Hold between SCLK assert then LRCLK deassert
or
Hold between LRCLK deassert then SCLK assert
SDI to SCLK deassert setup time
SDI from SCLK deassert hold time
SCLK assert to SDO delay time
SDO from SCLK assert hold time
Note:
t
i2s_clk
is programmable by the user.
Symbol
t
clk_per
t
clk_high
t
clk_low
t
clkrf
t
LRd
t
LRh
t
SDIs
t
SDIh
t
SDOd
t
SDOh
Min
-
-
-
1
-
0
12
0
-
1
Typ
t
i2s_clk
(t
i2s_clk
) / 2
(t
i2s_clk
) / 2
4
-
-
-
-
-
-
Max
-
-
-
8
3
-
-
-
9
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
clk_per
t
clk_high
t
clk_low
t
clkrf
SCLK
t
LRd
t
LRh
LRCLK
t
SDIs
t
SDIh
t
SDOh
SDI
t
SDOd
SDO
Figure 35. Inter-IC Sound (I
2
S) Timing Measurement
50
©
Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4
CIRRUS [ CIRRUS LOGIC ]
