EP9315
Enhanced Universal Platform SOC Processor
AC’97
Parameter
ABITCLK input cycle time
ABITCLK input high time
ABITCLK input low time
ABITCLK input rise/fall time
ASDI setup to ABITCLK falling
ASDI hold after ABITCLK falling
ASDI input rise/fall time
ABITCLK rising to ASDO / ASYNC valid, C
L
= 55 pF
ASYNC / ASDO rise/fall time, C
L
= 55 pF
Symbol
t
clk_per
t
clk_high
t
clk_low
t
clkrf
t
s
t
h
t
rfin
t
co
t
rfout
Min
-
36
36
2
10
10
2
2
2
Typ
81.4
-
-
-
-
-
-
-
-
Max
-
45
45
6
-
-
6
15
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
clk_high
t
clk_per
ABITCLK
t
clkrf
t
clkrf
t
clk_low
t
h
t
s
t
rfin
ASDI
ASDO
t
rfout
t
co
ASYNC
t
rfout
Figure 36. AC ‘97 Configuration Timing Measurement
t
co
t
co
t
rfout
DS638PP4
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Copyright 2005 Cirrus Logic (All Rights Reserved)
51
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