Figure 40. 352 PIN BGA PINOUT
1
Y
HSYNC
W
V
U
T
R
P
P[12]
P[16]
AD[0]
DA[8]
AD[2]
AD[4]
2
DD[1]
P[9]
P[11]
P[15]
BLANK
AD[1]
DA[10]
3
DD[12]
DD[0]
P[8]
P[10]
P[13]
P[17]
4
P[2]
P[5]
DD[15]
P[7]
SPCLK
P[14]
5
6
7
8
9
10
AD[8]
11
IDEDA[
0]
12
DTRN
TCK
TDI
13
TDO
TMS
GND
NC
CVDD
CVDD
14
15
16
ASDO
17
SFRM1
INT[3]
RTSN
18
19
20
57
AD[15] DA[6] DA[4]
P[3]
DD[13]
P[6]
DA[7] DA[5]
P[1]
P[4]
AD[10
DA[1]
]
AD[11
AD[9]
]
AD[1 AD[12
DA[2]
4]
]
P[0]
AD[13
DA[3]
]
RVDD
CVD
V_CSY DD[1
GND
D
NC
4]
RVDD
CVD
RVD
GND
D
D
RVD
D
CVD
D
GND
GND
GND
GND
GND
GND
RVD
D
GND
GND
CVD
D
CVD CVD
D
D
RVDD
GND
GND
GND
GND
GND
GND
EP9315
Enhanced Universal Platform SOC Processor
BOOT[0] EEDAT
EECLK
RDLED USBP[1] ABITCLK
Y
SLA[1]
USBP[0]
SLA[0]
CTSN
TXD[1]
RXD[2]
W
TXD[0]
V
IDECS1 IDEDA[
N
1]
IDECS0 IDEDA[
N
2]
DA[0]
GND
SCLK1 GRLED
ASYNC SSPTX1 INT[2]
SSPRX1
GND
GND
INT[1]
INT[0]
RVDD
RVDD
DSRN BOOT[1]
GND
RVDD
PWMO
USBM[0] RXD[1]
UT
USBM[1
RXD[0]
]
RVDD
RVDD
GND
GND
CVDD
CVDD
CVDD
RVDD
ROW[1]
U
ROW[4]
T
TXD[2] ROW[2]
ROW[0] ROW[3]
XTALI
XTALO
COL[4]
COL[5]
SYM
RTCXTA
LI
PLL_GN
ROW[5]
R
D
ROW[7]
P
COL[2]
CSN[0]
PRSTN
SXP
YM
XP
N
M
L
K
J
H
©
Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4
DA[9] BRIGHT RVDD
AD[3]
AD[5]
CVDD
CVDD
GND
RVDD
GND
PLL_VD
ROW[6]
D
COL[0]
COL[3]
COL[1]
COL[6]
N
DA[13]
M
AD[7]
L
DA[18]
K
AD[22]
J
DA[21]
H
G
F
DQMN[
3]
DA[12] DA[11]
DA[14]
AD[6]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DA[17] DA[16] DA[15]
DA[20] AD[21] DA[19]
DQMN[ DQMN[ DQMN[2
0]
1]
]
CASN
RASN
COL[7] RSTON
SYP
XM
SXM
YP
SDCSN[
CVDD
2]
RVDD
RVDD
GND
RTCXTA ADC_V ADC_G
LO
DD
ND
SDCSN[ SDCSN[ SDWE
SDCLK
0]
1]
N
SDCSN[
DA[22] DA[24] AD[25]
3]
DA[23] DA[26] CSN[6]
DA[25] DD[11]
SDCLK
EN
RVDD
CVDD
GND
GND
RVDD
CVDD
CVDD
GND
GND
RVDD EGPIO[7]
GND
ASDI
WP
EGPIO[2]
DIOWN
EGPIO[ EGPIO[1 EGPIO[11
G
9]
0]
]
EGPIO[ EGPIO[6
EGPIO[8]
F
4]
]
EGPIO[ EGPIO[3
EGPIO[5]
E
0]
]
E
AD[23]
D
AD[24]
AD[19] DD[9] DD[5]
AD[16 MIIRXD[ MIITXD[
TXEN
]
2]
3]
MCWAI MCDAE MCADE EGPIO[
TN
NN
NN
14]
MCD2
VS1
CLD
13
USBM[2] ARSTN DIORN EGPIO[1]
D
C
CSN[1] CSN[3] AD[20] DA[29]
B
CSN[2] DA[31] DA[30] DA[27]
A
CSN[7] DA[28] AD[18]
1
2
3
DD[8]
4
DD[10] DD[6] DD[2] MDC
DD[7] DD[3] WRN MDIO
DD[4]
5
MIITXD[
MIIRXD[
READY
TXCLK
0]
3]
MIIRXD[
MIITXD[
RXERR
1]
1]
CRS
MCDIR MCELN IORDN MCWRN USBP[2] IORDY DMACKN
C
MCD1
VS2
14
EGPIO[1
MCBVD
MCRDN WAITN
MCEHN
3]
2
TRSTN
B
RXCL MIIRXD[ RXDVA MIITXD[
AD[1
TXERR
RDN
K
0]
L
2]
7]
6
7
8
9
10
11
12
MCRESE
MCBVD MCREG EGPIO[1 EGPIO[
A
IOWRN
TN
1
N
2]
15]
15
16
17
18
19
20
CIRRUS [ CIRRUS LOGIC ]
