EP9315
Enhanced Universal Platform SOC Processor
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
C3
C4
AD[20]
DA[29]
H5
H8
CVDD
GND
N15
N16
N17
N18
N19
N20
P1
GND
GND
V15
V16
V17
V18
V19
V20
W1
SSPTX1
INT[2]
RTSN
USBP[0]
CTSN
TXD[0]
P[12]
C5
DD[10]
DD[6]
H9
GND
XTALO
COL[0]
COL[1]
COL[2]
AD[4]
C6
H10
H11
H12
H13
H16
H17
H18
H19
H20
J1
GND
C7
DD[2]
GND
C8
MDC
GND
C9
MIIRXD[3]
TXCLK
MIITXD[0]
READY
MCD2
GND
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
RVDD
RTCXTALO
ADC_VDD
ADC_GND
XP
P2
DA[10]
DA[9]
W2
P[9]
P3
W3
DD[0]
P4
BRIGHT
RVDD
RVDD
RVDD
RVDD
XTALI
PLL_VDD
ROW[6]
ROW[7]
AD[2]
W4
P[5]
P5
W5
P[3]
MCDIR
MCELN
IORDN
MCWRN
USBP[2]
IORDY
DMACKN
AD[24]
P6
W6
DA[7]
DA[21]
DQMN[0]
DQMN[1]
DQMN[2]
GND
P15
P16
P17
P18
P19
P20
R1
W7
DA[5]
J2
W8
AD[11]
AD[9]
J3
W9
J4
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
IDECS1N
IDEDA[1]
TCK
J5
J8
GND
J9
GND
TMS
D2
DA[25]
J10
J11
J12
J13
J16
J17
J18
J19
J20
K1
GND
R2
AD[1]
EECLK
SCLK1
GRLED
INT[3]
SLA[1]
SLA[0]
RXD[2]
HSYNC
DD[1]
D3
DD[11]
GND
R3
P[17]
D4
SDCLKEN
AD[19]
GND
R4
P[14]
D5
GND
R5
RVDD
RVDD
GND
D6
DD[9]
CVDD
RTCXTALI
XM
R6
D7
DD[5]
R7
D8
AD[16]
R8
CVDD
CVDD
GND
D9
MIIRXD[2]
MIITXD[3]
TXEN
YP
R13
R14
R15
R16
R17
R18
R19
R20
T1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
YM
Y2
AD[22]
DA[20]
AD[21]
DA[19]
RVDD
GND
RVDD
RVDD
ROW[0]
ROW[3]
PLL_GND
ROW[5]
DA[8]
Y3
DD[12]
P[2]
MCWAITN
MCDAENN
MCADENN
EGPIO[14]
WP
K2
Y4
K3
Y5
AD[15]
DA[6]
K4
Y6
K5
Y7
DA[4]
K8
Y8
AD[10]
DA[1]
USBM[2]
ARSTN
DIORN
EGPIO[1]
AD[23]
K9
GND
Y9
K10
K11
K12
K13
K16
K17
K18
K19
K20
L1
GND
T2
BLANK
P[13]
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
AD[8]
GND
T3
IDEDA[0]
DTRN
TDO
GND
T4
SPCLK
V_CSYNC
DD[14]
GND
GND
T5
E2
DA[23]
CVDD
SYM
T6
BOOT[0]
EEDAT
ASDO
SFRM1
RDLED
USBP[1]
ABITCLK
E3
DA[26]
T7
E4
CSN[6]
GND
SYP
T8
CVDD
RVDD
GND
E5
SXM
T9
E6
GND
SXP
T10
T11
T12
E7
CVDD
DA[18]
DA[17]
GND
E8
CVDD
L2
RVDD
DS638PP4
©Copyright 2005 Cirrus Logic (All Rights Reserved)
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