PIC16F616/16HV616
TABLE 2-2:
Addr
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
—
TRISC
—
—
PCLATH
INTCON
PIE1
—
PCON
—
OSCTUNE
ANSEL
PR2
—
—
WPUA
(2)
IOCA
—
—
SRCON0
SRCON1
—
—
—
ADRESL
ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register)
RAPU
(1)
PIC16F616/16HV616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Name
xxxx xxxx 17, 104
1111 1111 12, 104
0000 0000 17, 104
INTEDG
(1)
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 11, 104
xxxx xxxx 17, 104
Indirect Data Memory Address Pointer
—
Unimplemented
—
Unimplemented
Unimplemented
—
GIE
—
—
PEIE
ADIE
—
T0IE
CCP1IE
Write Buffer for upper 5 bits of Program Counter
INTE
C2IE
RAIE
C1IE
T0IF
—
INTF
TMR2IE
RAIF
TMR1IE
—
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111 25, 104
—
—
--11 1111 33, 104
—
—
—
—
---0 0000 17, 104
0000 0000 13, 104
-000 0-00 14, 104
—
—
Unimplemented
—
Unimplemented
—
ANS7
—
ANS6
—
ANS5
TUN4
ANS4
TUN3
ANS3
TUN2
ANS2
TUN1
ANS1
TUN0
ANS0
—
—
—
—
—
POR
BOR
---- --qq 16, 104
—
—
---0 0000 23, 104
1111 1111 26, 104
1111 1111 47, 105
—
—
—
—
Timer2 Module Period Register
Unimplemented
Unimplemented
—
—
Unimplemented
Unimplemented
SR1
SRCS1
SR0
SRCS2
C1SEN
—
C2REN
—
PULSS
—
PULSR
—
—
—
—
—
WPUA5
IOCA5
WPUA4
IOCA4
—
IOCA3
WPUA2
IOCA2
WPUA1
IOCA1
WPUA0
IOCA0
--11 -111 27, 105
--00 0000 27, 105
—
—
—
—
SRCLKEN
0000 00-0 59, 105
—
00-- ---- 59, 105
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
—
ADCS2
ADCS1
ADCS0
—
—
—
—
xxxx xxxx 72, 105
-000 ---- 71, 105
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’,
u
= unchanged,
x
= unknown,
q
= value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
DS41288A-page 10
Preliminary
©
2006 Microchip Technology Inc.
CIRRUS [ CIRRUS LOGIC ]
