GMSK Modem
CMX589A
Figure 10: Typical Transmit Eye Patterns
Figure 11: Tx Output Spectrum (Random Data)
4.4 Data Formats
The receive section of the CMX589A works best with data which has a reasonably random structure --the
data should contain approximately the same number of ‘ones’ as ‘zeroes’ with no long sequences (>100 bits)
of consecutive ones or zeroes. Also, long sequences (>100 bits) of 10101010 ... patterns should be avoided.
For this reason, it is recommended that data be made random in some manner before transmission, for
example by exclusive-ORing it with the output of a binary pseudo-random pattern generator.
Where data is transmitted in bursts, each burst should be preceded by a preamble designed to allow the
receive modem to establish timing and level lock as quickly as possible. This preamble for BT=0.3 should be
at least 16 bits long, and should preferably consist of alternating pairs of ones and zeros i.e.
110011001100....; the eye of pattern 10101010 .... has the most gradual slope and will yield poor peak levels
for the Rx circuits. For BT=0.5 the eye pattern of 10101010... has reduced intersymbol interference and may
be used as the preamble (DC Acq pin should be held high during preamble). See Figure 5.
4.5 Acquisition and Hold Modes
The RXDCacq and PLLacq inputs must be pulsed High for about 16 bits at the start of reception to ensure that
the DC measurement and timing extraction circuits lock-on to the received signal correctly. Once lock has
been achieved, the above inputs should be taken Low again.
In most applications, there will be a DC step in the output voltage from the receiver FM discriminator due to
carrier frequency offsets as channels are changed or when the remote transmitter is turned on.
The CMX589A can tolerate DC offsets in the received signal of at least ±10% of VDD with respect to VBIAS
,
(measured at the Rx Feedback pin). However, to ensure that the DC offset compensation circuit operates
correctly and with minimum delay, the Low to High transition of the RXDCacq and PLLacq inputs should occur
after the mean input voltage to the CMX589A has settled to within about 0.1V of its final value.
Note: This can place restrictions on the value of any series signal coupling capacitor.
ã 2002 CML Microsystems Plc
14
D/589A/4
CMLMICRO [ CML MICROCIRCUITS ]
