V23 / Bell 202 Modem
CMX624
1.5.12 ‘C-BUS’ Registers
Write Only ‘C-BUS’ Registers
Addr
$01
$E0
$E1
Reg.
RESET
7
6
N/A
TXON o/p:
0 = Off
1 = On
Tone or
FSK
o/p:
0 = Off.
1 = On.
5
N/A
Relay Drive:
0 = o/c
1 = Pull low
Reserved,
set to 0
Command Data Byte Bits
4
3
N/A
0 = Zero
Power
1 = Normal
0 = DTMF
1 = Single
tone
N/A
Stop bits:
0 = 1 bit
1 = 2 bits
Reserved,
set to 0
2
N/A
Parity:
0 = None
1 = Parity
Reserved,
set to 0
1
N/A
Parity:
0 = Odd
1 = Even
Reserved,
set to 0
0
N/A
Data bits:
0 = 8 bits
1 = 7 bits
Set Detect:
0 = FSK/CP
1 = 2100Hz
N/A
FSK mode:
SETUP
0 = V.23
1 = Bell 202
Tx Mode:
TX
TONES
0 = FSK.
1 = Tones.
$E3
$E7
TX
DATA
FSK
MODE
IRQ
MASK
D7
D6
0 = Rx Sync Rx Equal:
1 = Async
0 = Off
1 = On
Reserved,
Set to 0
Reserved,
Set to 0
D5
0 = Rx Call
Progress
1 = Rx FSK
Ring Detect
Change
D4
0 = Rx 75 /
150 bps
1 = 1200
Reserved,
Set to 0
D3
0 = Tx Sync
1 = Async
D2
Tx o/p level:
0 = Normal
1 = +3dB
Rx Data
ready
D1
FSK
enable:
0 = Off
1 = On
(Tx & Rx)
Tx Data
underflow
$EE
Rx Data
overflow
D0
0 = Tx 75 /
150 bps
1 = 1200 or
DTMF
Tx Data
ready
Read Only ‘C-BUS’ Registers
Addr
$EA
$EF
Reg.
RX
DATA
FLAGS
7
D7
Bad Rx
Parity
6
D6
Ring Detect
5
D5
Ring Detect
Change **
Reply Data Byte Bits
4
3
D4
Rx Energy
or 2100Hz
detect.
D3
Rx Data
overflow **
2
D2
Rx Data
ready **
1
0
D1
D0
Tx Data
Tx Data
underflow ** ready **
** See notes 2 and 3
Notes:
1.
Accessing the RESET Register over the ‘C-BUS’ clears all of the bits in the SETUP, TX TONES,
TX DATA, FSK MODE and IRQ MASK registers, and bits 0-3 and 5 of the FLAGS Register to
‘0’. This will set the device into Zero Power mode. Note that this is a single-byte ‘C-BUS’
transaction consisting solely of the address byte value $01.
Note that putting the device in Zero Power mode by directly setting SETUP Bit 4 to ‘0’ does not
clear the other register bits. Care should be taken before re-enabling the device that the other
bits are set so as to prevent undesired transient operation. In particular, bit 6 of the TXTONES
Register should be set to ‘0’ to prevent modulation of the transmitter output.
2.
3.
4.
5.
6.
If any of bits 0, 1, 2, 3 or 5 of the FLAGS Register is ‘1’ and the corresponding bit of the IRQ
MASK Register is also ‘1’ then the IRQN output of the CMX624 will be pulled low.
Bit 5 (Ring Detect Change) of the FLAGS Register is set on every ‘0’ to ‘1’ or ‘1’ to ‘0’ change of
bit 6 (Ring Detect).
Clearing bit 4 of the SETUP Register puts the CMX624 into the Zero Power mode by turning off
all blocks except for the ‘C-BUS’ interface and Ring Detector circuit.
Reading the FLAGS Register clears the IRQN output and also clears bits 0, 1, 2, 3 and 5 of the
FLAGS Register.
FLAGS Register (bit 4) is ‘1’ whenever the received signal being looked for is detected and ‘0’
when both signals are absent. IRQ MASK Register (bit 4) is normally set to ‘0’ - but can be set
to ‘1’ to enable interrupts on the IRQN output. In the latter case, IRQN will be continuously
pulled to ‘0’ whilst Rx Energy or 2100Hz are present. This may be useful for device evaluation
purposes.
2003 CML Microsystems Plc
14
D/624/7
CMLMICRO [ CML MICROCIRCUITS ]
