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CMX624 参数 Datasheet PDF下载

CMX624图片预览
型号: CMX624
PDF下载: 下载PDF文件 查看货源
内容描述: V.23 /贝尔202调制解调器 [V.23 / Bell 202 Modem]
分类和应用: 调制解调器
文件页数/大小: 26 页 / 702 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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V23 / Bell 202 Modem  
CMX624  
In the transmit direction, the level on the 4-wire line is determined by the level at the TOP pin, the gain  
of the Output Buffer Amplifier, a loss of nominally 6dB due to the line termination resistor R15, and the loss  
in the transformer.  
The TOP pin signal level is proportional to V  
control bit (bit 2) of the FSK Mode Register.  
and is also affected by the setting of the Tx o/p level  
DD  
Assuming that the Tx o/p level control bit is set to ‘1’ (giving a FSK signal level of -3dB wrt 775mVrms at  
the TOP pin when V = 5.0V) and that there is 1dB loss in the transformer, then:  
DD  
Tx FSK 4-wire line level = -(3 +6 +1) + 20 x LOG10(2 x R14 / R13) + 20 x LOG10(V / 5.0) dBm  
DD  
For example, to generate a nominal Tx FSK line level of -9dBm, R13 should be 180kwhen V = 5.0V,  
DD  
falling to 120kat 3.3V.  
2-Wire Line Interface  
Figure 8b shows an interface circuit suitable for connection to a 6002-wire line. The circuit also shows  
how a relay may be driven from the RLYDRV pin. Note that when the CMX624 is powered from less than  
5.0V, buffer circuitry will be required to drive a 5V relay.  
Note ac and dc loads and line protection not shown for clarity.  
R11  
R12  
R13  
R14  
See text  
100kΩ  
See text  
R15  
R16  
R17  
C11  
C12  
C13  
C14  
220pF  
330pF  
10nF  
600Ω  
120kΩ  
100kΩ  
100nF  
100kΩ  
Resistors ±1%, capacitors ±20%  
Figure 8b 2-Wire Line Interface Circuit  
This circuit includes a 2-wire to 4-wire hybrid circuit, formed by R11, R15, R16, R17, C13 and the  
impedance of the line itself, which ensures that the modem receive input and transmit output paths are  
both coupled efficiently to the line, while minimising coupling from the modem’s transmit signal into the  
receive input.  
The values of R11 and R13 should be calculated in the same way as for the 4-wire interface circuit of  
Figure 8a.  
2003 CML Microsystems Plc  
16  
D/624/7