CMX644AD5 参数 Datasheet PDF下载

V22 and Bell 212A Modem

CMX644A

1.5.2

UART

This block connects the µC, via the ‘C-BUS’ interface, to the received data from the PSK Demodulator and to

the transmit data input to the PSK Modulator.

As part of this function, the block can be programmed to convert data to be transmitted from 7 or 8-bit bytes

to asynchronous data characters, adding Start and Stop bits and - optionally - a parity bit to the data before

passing it to the PSK Modulator. Similarly, in the receive direction it can extract data bits from asynchronous

characters coming from the PSK Demodulator, stripping off the Start and Stop bits and performing an optional

Parity check on the received data before passing the result over the ‘C-BUS’ to the µC. Bits 0-5 of the UART

MODE Register control the number of Stop and Data bits and the Parity options for both receive and transmit

directions.

Data to be transmitted should be loaded by the µC into the TX DATA BYTE Register when the Tx Data Ready

bit (bit 1) of the FLAGS Register goes high. It will then be treated by the Tx UART block in one of two ways,

depending on the setting of bit 5 of the UART MODE Register:

If bit 5 of the UART MODE Register is ‘0’ (‘Sync’ mode) then the 8 bits from the TX DATA BYTE

Register will be transmitted sequentially LSB (D0) first.

If bit 5 of the UART MODE Register is ‘1’ (‘Async’ mode) then the 7 or 8 bits will be transmitted as

asynchronous data characters according to the following format:

One Start bit (Space).

7 or 8 Data bits from the TX DATA BYTE Register (D0-D6 or D0-D7) as determined by bit 0

of the UART MODE Register. LSB (D0) transmitted first.

Optional Parity bit (even or odd parity) as determined by bits 1 and 2 of the UART MODE

Register.

Zero, One or Two Stop bits (Mark) as determined by bits 3 and 4 of the UART MODE

Register.

In both cases data will only be transmitted if bit 6 of the TX PSK MODE Register is set to ‘1’.

Failure to load the TX DATA BYTE Register with a new value when required will result in bit 2 (TX DATA

UNDERFLOW) of the FLAGS Register being set to ‘1’ and a continuous Mark (‘1’) signal will then be

transmitted until a new value is loaded into TX DATA BYTE Register.

Figure 4a Transmit UART Function (Async)

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2000

Consumer Microcircuits Limited

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