Baseband Signal Processor
12
MX829 PRELIMINARY INFORMATION
5.2.5 CONTROL 3 / IRQ ENABLE Register (Hex address $40)
This register is a mixture of control bits and interrupt mask bits, as detailed below:
Bit 7
1200/2400
(Bit 6)
TXIDLEM
(Bit 5)
RXDATAM
(Bit 4)
TXDATAM
(Bit 3)
RX SYNC WORD
PRIME
(Bit 2)
SYNT PRIME
(Bit 1)
SYNC PRIME
(Bit 0)
Not used, set to zero.
When this bit is "1", the MSK Rx and Tx are set to operate at 1200 baud.
When this bit it "0", the MSK Rx and Tx are set to operate at 2400 baud.
When this bit is "1", the TXIDLE interrupt will be gated out to the
IRQ
pin.
When this bit is "0", the TXIDLE interrupt will be inhibited. This bit has no effect on the contents of the
STATUS register.
When this bit is "1", the RXDATA interrupt will be gated out to the
IRQ
pin.
When this bit is "0", the RXDATA interrupt will be inhibited. This bit has no effect on the contents of
the STATUS register.
When this bit is "1", the TXDATA interrupt will be gated out to the
IRQ
pin.
When this bit is "0", the TXDATA interrupt will be inhibited. This bit has no effect on the contents of
the STATUS register.
When this bit is set to "1", it enables the RX SYNC WORD detection.
It is cleared/disabled when a SYNC, SYNT, or RX SYNC WORD is detected.
It may also be cleared/disabled by writing "0" directly to this bit.
When this bit is set to "1", it enables the SYNT detection.
It is cleared/disabled when a SYNC, SYNT, or RX SYNC WORD is detected.
It may also be cleared/disabled by writing "0" directly to this bit.
When this bit is set to "1", it enables the SYNC detection.
It is cleared/disabled when a SYNC, SYNT, or RX SYNC WORD is detected.
It may also be cleared/disabled by writing "0" directly to this bit.
5.2.6 TXDATA Register (Hex Address $43)
This is the Tx data output register. It is double buffered, thus giving the user up to 8 bit periods to load in the next 8 bits.
MSK data is transmitted immediately it is loaded if the transmitter is idle. Data is transmitted in 8-bit bytes, bit 7 (MSB) will
be transmitted first.
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