AccessRunner
Pin Name
R_INTER_DATA
I/O
O
Description
Controller-less ADSL Modem Device Set for PCI Applications
Receive Interleaved Data Bit Output
Clocked at BIT_CLOCK rate.
R_INTER_SUPER#
PCI CONTROLLER INTERFACE
D[15:0]
O
Receive Interleaved Data Bit Output Superframe Qualifier
I/O
PCI Controller Interface Data Bus
16-bit input/output bus to send/receive data to/from PCI controller.
A[9:0]
I
PCI Controller Interface Address Bus
10-bit input bus to receive address from PCI controller.
WR#
RD#
CS#
IRQ[1:0]#
MISCELLANEOUS
RST#
I
I
I
O
Data Write Enable
Data Read Enable
Chip Select
Programmable Interrupts
I
Global Chip Reset
When low, puts chip into reset condition.
MCLK
I
High-speed Master Clock
Connect to 35.328 MHz VCXO, which is 16 times the maximum Nyquist rate.
VXCO_CTRL
O
Oversampled VCXO analog control voltage
MON_OUT
MON_CLK
O
O
1-bit serial D/A output used for constellation monitoring
Serial Monitor Clock
Operates at 138 kHz.
MON_DONE
DMCK_ALT
LTR
NTR
NTRCTL
TXSOC0
TXSOC1
RXSOC0
RXSOC1
PWR_DN
POWER AND GROUND
VDD
VDDcore
GND
VGG
O
I
O
I/O
I
I
I
O
O
I
New Symbol Constellation Qualifier
External 2x Clock
8 kHz Local Timing Reference
8 kHz Network Timing Reference
Network Timing Reference I/O Control
TC0 Block Transmit Start of Cell.
TC1 Block Transmit Start of Cell.
TC0 Block Receive Start of Cell
TC1 Block Receive Start of Cell
Power Down Control Pin
3.3V Power (I/O)
2.5V Power (Core)
Ground
I/O Clamp Power Supply (connect to 5 volt supply for 5 volt tolerance)
12
Conexant
Proprietary Information
Doc. No. 100394B
October 19, 1999
CONEXANT [ CONEXANT SYSTEMS, INC ]
