Controller-less ADSL Modem Device Set for PCI Applications
AccessRunner
11627 ADSL DMT Data Pump Hardware Pins and Signals
The pin assignments for the 11627 are shown in Figure 5 and listed in Table 3. The signals are defined in
VDD
VDDcore
VDDcore
GND
VDDcore
GND
169
168
176
175
174
173
172
171
170
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
GND
DAC_CLK
FILTER_CLK
T_FAST_BYTE#
T_INTER_BYTE#
R_CLK_AS1
NC
NTR
GND
VDD
R_CLK_AS0
NC
T_CLK_LS1
T_DAT_LS1
T_CLK_LS0
T_DAT_LS0
BIT_CLOCK
GND
GND
GND
TXSOC0
TLXCK_EN
TXSOC1
AFE_STR#
VDDcore
VDDcore
VDD
GND
NTRCTL
DMCK_ALT
R_INTER_SUPER#
R_INTER_DATA
R_FAST_SUPER#
R_FAST_FRAME#
GND
VDD
R_NCO_LS0
R_NCO_LS1
R_NCO_AS0
R_NCO_AS1
R_DAT_AS0
R_DAT_AS1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDDcore
GND
RX[15]
RX[14]
RX[13]
RX[12]
RX[11]
RX[10]
TX[15]
TX[14]
TX[13]
TX[12]
TX[11]
TX[10]
RX[9]
RX[8]
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
TX[9]
TX[8]
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
VDD
GND
VDD
GND
GND
GND
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD
GND
RX[1]
RX[0]
ADC_CLK
D[0]
D[1]
D[2]
D[3]
D[4]
VDD
GND
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
VDD
VDDcore
VDDcore
GND
GND
GND
D[15]
VGG
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
VDDcore
GND
A[9]
WR#
VDD
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
80
81
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
R_DAT_LS0
R_CLK_LS1
R_DAT_LS1
NC
RXSOC0
RXSOC1
R_CLK_LS0
VCXO_CTRL
MON_DONE
GND
GND
VDD
NC
IRQ[1]#
IRQ[0]#
82
83
NC
VDDcore
VDDcore
VDDcore
VDDcore
VDDcore
VDD
MON_OUT
CLIP#
RST#
MCLK
VDD
GND
NC
GND
GND
GND
GND
GND
GND
NC
LTR
NC
NC
84
85
86
87
RD#
CS#
MON_CLK
PWR_DN
GND
88
DSL015_005
Figure 5. 11627 Pinout Diagram
Doc. No. 100394B
October 19, 1999
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