2.0 Circuit Description
2.4 Transmitter
CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
2.4.5 Test Pattern Generation
The transmit test pattern generation circuitry overwrites the transmit data with
various test patterns and permits logical and frame-bit error insertion. This
feature is particularly useful for system diagnostics, production testing, and test
equipment applications. The test pattern can be a framed or unframed PRBS
pattern. The PRBS patterns available include 2E11-1, 2E15-1, 2E20-1, and
2E23-1. Each pattern can optionally include Zero Code Suppression (ZCS). Error
insertion includes LCV, BPV, Ft, CRC4, CRC6, COFA, PRBS, Fs, MFAS, and
CAS.
The Transmit Test Pattern Configuration register [TPATT; addr 076] controls
the test pattern insertion circuit. TPATT controls the PRBS pattern (TPATT[1:0])
bits), ZCS setting (ZLIMIT bit), T1/E1 framing (FRAMED bit), and starting and
stopping transmission (TPSTART bit).
Patterns are generated in accordance with ITU–T O.150 (10/92), O.151
(10/92), and O.152 (10/92). Enabling ZLIMIT modifies the inserted pattern by
limiting the number of consecutive zeros. For the 2E11-1 or 2E15-1 PRBS
patterns, eight or more zeros will not occur with ZLIMIT enabled. For the 2E20-1
or 2E23-1 PRBS patterns, 15 or more zeros will not occur with ZLIMIT enabled.
Note that the QRSS pattern is a 2E20-1 PRBS with ZLIMIT enabled. This
function is performed according to ANSI T1.403 and ITU–T O.151 (10/92).
Frame bit positions can be preserved in the output pattern by enabling
FRAMED. In T1 mode, this prevents the test pattern from overwriting the frame
bit which occurs every 193 bits. In E1 mode with FRAMED enabled, the test
pattern does not overwrite time slot 0 data (FAS and NFAS words) and time slot
16 (CAS signalling word) if CAS framing is also selected. CAS framing is
selected by setting TFRAME[3] to 1 in the Transmit Configuration register
[TCR0; addr 070]. The test pattern is stopped during these bit periods according
to ITU-T O.151, (10/92). If FRAMED is disabled, the test pattern is transmitted in
all time slots.
2.4.6 Transmit Error Insertion
The Transmit Error Insert register [TERROR; addr 073] controls error insertion
during pattern generation. Writing one to a TERROR bit injects a single
occurrence of the respective error on TPOSO/TNEGO and XTIP/XRING
outputs; writing a zero has no effect. Multiple transmit errors can be generated
simultaneously. Periodic or random bit error rates can also be emulated by
software control of the error control bit. Note that injected errors affect the data
sent during a Framer or Analog Loopback [FLOOP or ALOOP; addr 014].
Line Code Violations (LCV) are inserted via the TVERR bit of the TERROR
register. In T1 mode, if TVERR is set, a BPV is inserted between two consecutive
ones. TVERR is latched until the BPV is inserted into the transmit data stream,
and then cleared. In E1 mode with HDB3 selected, two consecutive BPVs of the
same polarity are inserted. This is registered as a single LCV for the receiving E1
equipment.
Ft, FPS, and FAS bit errors are inserted using the TFERR bit in the TERROR
register. TFERR commands a logical inversion of the next frame bit transmitted.
CRC4 (E1) and CRC6 (T1) bit errors are inserted using the TCERR bit in the
TERROR register. TCERR commands a logical inversion of the next CRC bit
transmitted.
2-50
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
