CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
2.0 Circuit Description
2.4 Transmitter
Change Of Frame Alignments (COFAs) are controlled by the TCOFA and
BSLIP bits in the TERROR register. TCOFA commands a 1-bit shift in the
location of the transmit frame alignment by deleting (or inserting) a 1-bit position
from the transmit frame. During E1 modes, BSLIP determines which direction
the bit slip occurs. In T1 modes, only 1-bit deletion is provided. Note that TCOFA
alters extraction rate of data from transmit slip buffer; thus, repeated TCOFAs
eventually cause a controlled frame slip where one frame of data is repeated
(T1/BSLIP = 0), or where one frame of data is deleted (BSLIP = 1).
PRBS test pattern errors are inserted by TBERR in the TERROR register.
TBERR commands a single PRBS error by logically inverting the next PRBS
generator output bit.
Fs and MFAS errors are controlled by the TMERR bit in the TERROR
register. TMERR commands a single Fs bit error in T1, or MFAS bit error in E1
by logically inverting the next multiframe bit transmitted.
CAS Multiframe (MAS) errors are controlled by the TSERR bit in the
TERROR register. TSERR commands a single MAS pattern error by logically
inverting the first MAS bit transmitted.
2.4.7 In-Band Loopback Code Generation
The in-band loopback code generator circuitry overwrites the transmit data with
in-band codes of configurable value and length. These codes are sequences with
periods of 1 to 7 bits and may, in some applications, overwrite the framing bit.
The Transmit Inband Loopback Code Configuration register [TLB; addr 077]
controls the functions required for this operation.
A loopback code is generated in the transmit data stream by writing the
loopback code to the Transmit Inband Loopback Code Pattern register [LBP; addr
078], and then setting the Start Inband Loopback (LBSTART) and Loopback
Length (LB_LEN) bits in the Transmit Inband Loopback Code Configuration
register [TLB; addr 077]. The TLB register optionally allows the loopback code
to overwrite framing bits using the UNFRAMED bit. The LB_LEN provides
loopback code pattern lengths of 4 to 7 bits. Patterns of 2 or 3 bits can be achieved
by repeating the pattern in 4- or 6-bit modes, respectively. Framed or unframed all
ones or all zeros can also be achieved by setting the pattern to all zeros or all ones.
2.4.8 ZCS Encoder
The ZCS encoder encodes the single rail clock and data (unipolar) into dual rail
data (bipolar). The Transmit Zero Code Suppression Bits (TZCS[1,0]) in the
Transmitter Configuration register [TCR1; addr 071] selects ZCS and Pulse
Density Violation (PDV) enforcement options for TPOSO/TNEGO output pins.
TZCS supports the following: Alternate Mark Inversion (AMI); High Density
Bipolar of order 3 (HDB3); Bipolar with 8 Zero Suppression (B8ZS); Pulse
Density Violation (PDV); Unassigned Mux Code (UMC); and Bipolar with 7
Zero Suppression (B7ZS). Note that ZCS encoding, which alters data content, is
performed prior to the CRC calculation so the outgoing CRC is always correct.
The AMI line code requires at least 12.5 percent average ones density and no
more than 15 consecutive zeros. A one is encoded as either a positive or negative
pulse; a zero is the absence of a pulse. Two consecutive pulses of the same
polarity are referred to as a Bipolar Violation (BPV).
100054E
Conexant
2-51
CONEXANT [ CONEXANT SYSTEMS, INC ]
