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CX28398-22 参数 Datasheet PDF下载

CX28398-22图片预览
型号: CX28398-22
PDF下载: 下载PDF文件 查看货源
内容描述: 四核/ X16 /八路T1 / E1 / J1成帧器 [Quad/x16/Octal?T1/E1/J1 Framers]
分类和应用:
文件页数/大小: 305 页 / 1863 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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3.0 Registers
3.2 Global Control and Status Registers
CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
3.2 Global Control and Status Registers
Global registers are applicable to all framers in the CX28394 and CX28398. There are two sets of global
registers for the CX28395, one for each 8-framer group.
000—Device Identification (DID)
Read only value.
7
DID[7]
6
DID[6]
5
DID[5]
4
DID[4]
3
DID[3]
2
DID[2]
1
DID[1]
0
DID[0]
DID[7:4]
DID[3:0]
Device Revision—A value of 0x4 indicates the current revision.
Device ID—A value of 0x8 indicates the CX28398 or CX28395. A value of 0x4 indicates the
CX28394.
080—Framer Control Register (FCR)
Unused bits are reserved and should be written to 0.
7
GRESET
6
5
4
3
2
ONESEC_IO
1
SBIMODE[1]
0
SBIMODE[0]
GRESET
Global Reset —When written to 1 by the microprocessor, GRESET initiates an internal global
reset process which initializes all global control registers and certain control registers for all
framers to their default settings (see
The internal reset process takes a maximum of
15
µ
sec.
The processor must not write to the control registers until the reset process is complete.
GRESET remains active (1) during the reset process to allow the microprocessor to detect
reset completion. GRESET also indicates a reset operation triggered by power-up or by an
active low RST* pin. After GRESET initialization, the following is true:
• System bus outputs (RSIGO, RPCMO, and SIGFRZ) for all framers are three-stated.
• Programmable I/O pins are configured as inputs.
• Global control and framer control registers are set to their default values.
ONESEC_IO
Bidirectional ONESEC Input/Output Mode—Selects input or output mode for ONESEC
signal pin and controls the internal timer interval used for one-second status latching [LATCH;
addr 046]. When ONESEC is an output, SYSCLK is used to develop the one-second timer
interval output with an arbitrarily defined initial starting location. When ONESEC is an input,
the timer/latch interval is aligned to rising edge of ONESEC input. The system can apply
ONESEC input to define any length timer/latch interval up to 1 second, but not greater than 1
second.
0 = ONESEC input
1 = ONESEC output
3-8
Conexant
100054E