CX28398-22 参数 Datasheet PDF下载

CX28394/28395/28398

Quad/x16/Octal—T1/E1/J1 Framers

2.0 Circuit Description

2.4 Transmitter

2.4.1 External Transmit Data Link (CX28394 and CX28398 Only)

The External Data Link (DL3) allows the system to externally supply any bit(s) in

any time slot in all frames, odd frames or even frames, including T1 framing bits.

Pin access to the DL3 transmitter is provided through TDLCKO and TDLI. These

two pins serve as the TDL3 clock output (TDLCKO) and data input (TDLI). The

mode of the pins is selected using the TDL_IO bit in the Programmable

Input/Output register [PIO; addr 018].

Control of DL3 format is provided in two registers: External Data Link

Channel [DL3_TS; add 015] and External Data Link Bit [DL3_BIT; addr 016].

Transmit DL3 is set up by selecting the bit(s) [DL3_BIT], time slot [TS[4:0];

addr 015], and frames [EVEN/ODD; addr 015] to be overwritten, then enabling

the data link [DL3EN; addr 015]. Enabling the data link will start TDLCKO

gating the NRZ data provided on TDLI (see

NOTE:

DL3 signals are not provided on the CX28395. Therefore, DL3_TS must

be written to 00 to disable the DL3 transmitter and prevent transmit data

corruption.

Figure 2-21. Transmit External Data Link Waveforms

TDLCKO

TS8

TDLI

1

2

TS9

7

8

TS10

NOTE(S):

This example shows bits 1, 2, 7, and 8 of TS9 selected. Any combination of time slot bits can be selected.

2.4.2 Transmit Data Links

The XMTR contains two independent data link controllers (DL1, DL2), a

Performance Report Message (PRM) generator, and a Bit-Oriented Protocol

(BOP) transceiver. DL1 and DL2 can be programmed to send and receive HDLC

formatted messages in the Message Oriented Protocol (MOP) mode or

unformatted serial data over any combination of bits within a selected time slot or

F-bit channel. The PRM message generator can immediately or automatically

send one-second performance reports. The BOP transceiver can preemptively

transmit BOP messages, such as ESF Yellow Alarm.

2.4.2.1 Data Link

Controllers

DL1 and DL2 control serial data channels operating at multiples of 4 kbps up to

the full 64 kbps time slot rate by selecting a combination of bits from odd, even,

or all frames. Both data link controllers support ESF Facilities Data Link (FDL),

SLC-96 data link, Sa data link, Common Channel Signaling (CCS), Signaling

System #7 (SS7), ISDN LAPD channels, Digital Multiplexed Interface (DMI)

signaling in TS24, as well as the latest ETSI V and V signaling channels.

.51

.52

DL1 and DL2 each contain a 64-byte transmit buffer which function either as

programmable length circular buffers in transparent (unformatted) mode, or as

full-length data FIFOs in formatted (HDLC) mode.

100054E

Conexant

2-41