STC5230 参数 Datasheet PDF下载

Synchronous Clock for SETS

Data Sheet

STC5230 Pin Description

All I/O is LVCMOS, except for CLK0 and CLK8, which are LVPECL.

STC5230

Table 1: Pin Description

Pin Name

Vdd33

Pin

#

6,22,31,

44,59,61,

69,80,

87,97

9,18,27,

38,47,53,

60,65,84,

92

3,13,15,

20,29,35,

41,56,64,

67,71,78,

82,88,95

1, 76

75, 100

94

93

91

90

89

30

99

45

46

50

51

37

36

34

33

32

2

4

5

8

10

12

I

I

I

I

O

I

I

I

I

I

O

I/O

I/O

I/O

I/O

O

I

I

I

I

I

I

I/O

3.3V power input

Description

Vdd18

1.8V power input

Vss

Digital ground

AVdd18

AVss

TRST

TCK

TMS

TDI

TDO

RESET

MCLK

SPI_CS

SPI_SCK

SPI_SDI

SPI_SDO

EEP_SO

EEP_SI

EEP_SCK

EEP_CS

EVENT_INTR

REF1

REF2

REF3

REF4

REF5

REF6

1.8V analog power input

Analog ground

JTAG boundary scan reset, active low

JTAG boundary scan clock

JTAG boundary scan mode selection

JTAG boundary scan data input

JTAG boundary scan data output

Active low to reset the chip

Master clock input, 20 MHz

SPI bus chip select (CS)

SPI bus clock input (SCLK)

SPI bus data input (SDI)

SPI bus data output (SDO)

Optional external EEPROM SO

Optional external EEPROM SI

Optional external EEPROM SCK

Optional external EEPROM CS

event interrupt

Reference input 1

Reference input 2

Reference input 3

Reference input 4

Reference input 5

Reference input 6

Page 5 of 48

Rev: P01

Date: August 22, 2007

Preliminary

Data Sheet #:

TM102

© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice