P R E L I M I N A R Y
PIN DESCRIPTION
A20–A0
A-1
DQ15–DQ0
CE#f
CE1#s
CE2s
OE#
WE#
RY/BY#
UB#s
LB#s
CIOf
= 21 Address Inputs (Common)
= 2 Address Inputs (Flash)
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
= Chip Enable 1 (pSRAM)
= Chip Enable 2 (pSRAM)
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output
= Upper Byte Control (pSRAM)
= Lower Byte Control (pSRAM)
= I/O Configuration (Flash)
CIOf = V
IH
= Word mode (x16),
CIOf = V
IL
= Byte mode (x8)
= Hardware Reset Pin, Active Low
= Hardware Write Protect/
Acceleration Pin (Flash)
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
21
A20–A0
A-1
SA
CE#f
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
CIOf
RY/BY#
DQ15–DQ0
16 or 8
RESET#
WP#/ACC
V
CC
f
V
CC
s
V
SS
NC
8
Am49DL32xBG
July 19, 2002
CYPRESS [ CYPRESS SEMICONDUCTOR ]
