P R E L I M I N A R Y
CONNECTION DIAGRAM
73-Ball FBGA
Top View
A1
NC
A10
NC
Flash only
B1
NC
B5
NC
B6
NC
B10
NC
Pseudo
SRAM only
Shared
C1
NC
C3
A7
C4
D4
UB#
C5
D5
E5
RY/BY#
C6
D6
E6
A20
C7
A8
C8
A11
LB# WP#/ACC WE#
D2
A3
D3
A6
D7
A19
D8
A12
D9
A15
RESET# CE2s
E2
A2
E3
A5
E4
A18
E7
A9
E8
A13
E9
NC
F1
NC
F2
A1
F3
A4
F4
A17
F7
A10
F8
A14
F9
NC
F10
NC
G1
NC
G2
A0
G3
V
SS
G4
DQ1
G7
DQ6
G8
NC
G9
A16
G10
NC
H2
CE#f
H3
OE#
H4
DQ9
H5
DQ3
H6
DQ4
H7
J7
DQ12
H8
J8
DQ7
H9
J9
V
SS
DQ13 DQ15/A-1 CIOf
J2
CE1#s
J3
DQ0
J4
DQ10
J5
V
CC
f
J6
V
CC
s
K3
DQ8
K4
DQ2
K5
DQ11
K6
NC
K7
DQ5
K8
DQ14
L1
NC
L5
NC
L6
NC
L10
NC
M1
NC
M10
NC
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (TSOP, SO, PDIP, PLCC). The
package and/or data integrity may be compromised if
the package body is exposed to temperatures above
150°C for prolonged periods of time.
July 19, 2002
Am49DL32xBG
7
CYPRESS [ CYPRESS SEMICONDUCTOR ]
