CY2310ANZ
Switching Characteristics
[3]
Parameter
Duty Cycle
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Name
Maximum Operating Frequency
[2, 4]
Test Conditions
Measured at 1.5V
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
All outputs equally loaded
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Min.
45.0
0.9
0.9
1.0
1.0
1.0
1.0
Typ.
50.0
1.5
1.5
150
3.5
3.5
5
20
Max.
100
55.0
4.0
4.0
250
5.0
5.0
12
30
Unit
MHz
%
V/ns
V/ns
ps
ns
ns
ns
ns
= t
2
÷
t
1
Rising Edge Rate
[2]
Falling Edge Rate
[2]
Output to Output Skew
[2]
SDRAM Buffer LH Prop. Delay
[2]
SDRAM Buffer HL Prop. Delay
[2]
SDRAM Buffer Enable Delay
[2]
SDRAM Buffer Disable Delay
[2]
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.5V
1.5V
1.5V
All Outputs Rise/Fall Time
2.4V
0.4V
t
3
2.4V
0.4V
t
4
3.3V
0V
OUTPUT
Output-Output Skew
OUTPUT
1.5V
OUTPUT
t
5
1.5V
Notes:
3. All parameters specified with loaded outputs.
4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns
Document #: 38-07142 Rev. *B
Page 4 of 8
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