CY25811/12/14
Table 2. Spread% Selection
(continued)
XIN
(MHz)
20-24
24-28
28-32
FRSEL
M
M
M
S1 = 0
S0 = 0
±1.3
±1.2
±1.1
S1 = 0
S0 = M
±1.1
± 0.9
± 0.9
S1 = 0
S0 = 1
± 0.5
± 0.5
± 0.4
S1 = M
S0 = 0
± 0.4
± 0.4
± 0.3
S1 = 1
S0 = 1
–2.7
–2.5
–2.3
S1 = 1
S0 = 0
–1.9
–1.8
–1.7
S1 = M
S0 = 1
–1.7
–1.5
–1.4
S1 = 1
S0 = M
–0.6
–0.6
–0.5
S1 = M
S0 = M
0
0
0
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0” and
Middle “M”. With this 3-Level digital input logic, the 3-Level
Logic is able to detect 9 different logic states.
S0, S1 and FRSEL pins include an on chip 20K (10K/10K)
resistor divider. No external application resistors are needed
to implement the 3-Level logic levels as shown below:
Logic Level “0”: 3–Level logic pin connected to GND.
Logic Level “M”: 3–Level logic pin left floating (no connection).
Logic Level “1”: 3–Level logic pin connected to V
DD
.
illustrates how to implement 3–Level Logic.
LOGIC
LOW (0)
S0, S1
and
FRSEL
to VSS
LOGIC
MIDDLE (M)
S0, S1
and
FRSEL
UNCONNECTED
LOGIC
HIGH (H)
S0, S1
and
FRSEL
to VDD
VSS
Figure 1. 3–Level Logic
Modulation Rate
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax) and
minimum frequency of the clock (fmin) determine this band of
frequencies. The time required to transition from fmin to fmax
and back to fmin is the period of the Modulation Rate. The
Modulation Rate of SSCG clocks are generally referred to in
terms of frequency, or
fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
In the case of CY25811/2/4 devices, the (Spread Spectrum)
modulation Rate, fmod, is given by the following formula:
fmod = fin/DR
where; fmod is the Modulation Rate, fin is the Input Frequency
and DR is the Divider Ratio as given in
Notice that
Input Frequency Range is set by FRSEL.
Table 3. Modulation Rate Divider Ratios
FRSEL
0
1
M
Input Frequency Range
(MHz)
4 to 8
8 to 16
16 to 32
Divider Ratio
(DR)
128
256
512
Input and Output Frequency Selection
The relationship between input frequency versus output
frequency in terms of device selection and FRSEL setting is
given in
As shown, the input frequency range is
selected by FRSEL and is the same for CY25811, CY25812,
and CY25814. The selection of CY25811 (1x), CY25812 (2x)
or CY25814 (4x) determines the frequency multiplication at
the output (SSCLK, Pin 5) with respect to input frequency
(XIN, Pin-1).
Document #: 38-07112 Rev. *E
Page 3 of 11
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