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CY62148EV30LL-45ZSXI 参数 Datasheet PDF下载

CY62148EV30LL-45ZSXI图片预览
型号: CY62148EV30LL-45ZSXI
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K ×8)静态RAM [4-Mbit (512K x 8) Static RAM]
分类和应用:
文件页数/大小: 12 页 / 1007 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62148EV30 MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................... 55°C to +125°C
Supply Voltage to Ground
Potential ......................................... –0.3V to V
CC(max)
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
........................ –0.3V to V
CC(max)
+ 0.3V
DC Input Voltage
.....................–0.3V to V
CC(max)
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Operating Range
Product
Range
Ambient
Temperature
V
CC
2.2V to 3.6V
CY62148EV30 Industrial –40°C to +85°C
Electrical Characteristics
(Over the Operating Range)
Parameter
V
OH
V
OL
V
IH
V
IL
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Test Conditions
I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70V
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
> 2.70V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.2V to 2.7V For VFBGA and
TSOP II package
For SOIC package
V
CC
= 2.7V to 3.6V For VFBGA and
TSOP II package
For SOIC package
I
IX
I
OZ
I
CC
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power Down
Current — CMOS
Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CC(max),
I
OUT
= 0 mA,
CMOS levels
–1
–1
15
2
1
+1
+1
20
2.5
7
–0.3
0.8
–0.3
–1
–1
15
2
1
0.6
+1
+1
20
2.5
7
µA
µA
µA
mA
1.8
2.2
–0.3
45 ns
Min Typ
2.0
2.4
0.4
0.4
V
CC
+ 0.3V 1.8
V
CC
+ 0.3V 2.2
0.6
–0.3
0.4
Max
2.0
2.4
0.2
0.4
V
CC
+ 0.3V
V
CC
+ 0.3V
55 ns
Min Typ
Max
Unit
V
V
V
V
V
V
V
V
V
I
SB1
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V
f = f
max
(Address and Data Only),
f = 0 (OE and WE), V
CC
= 3.60V
I
SB2 [9]
Automatic CE
CE > V
CC
– 0.2V,
Power Down
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
Current — CMOS f = 0, V
CC
= 3.60V
Inputs
1
7
1
7
µA
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100
µs
ramp time from 0 to V
CC(min)
and 200
µs
wait time after V
CC
stabilization.
8. Under DC conditions the device meets a V
IL
of 0.8V (for V
CC
range of 2.7V to 3.6V) and 0.6V (for V
CC
range of 2.2V to 2.7V). However, in dynamic conditions
Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only. Please refer to
AN13470 for details.
9. Only chip enable (CE) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Document #: 38-05576 Rev. *F
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