CY62148E MoBL
®
Figure 7. Write Cycle No. 2
(CE Controlled)
t
WC
ADDRESS
t
SCE
t
SA
t
AW
t
PWE
WE
t
SD
DATA I/O
DATA VALID
t
HD
t
HA
CE
Figure 8. Write Cycle No. 3
(WE Controlled, OE LOW)
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
SD
DATA I/O
NOTE
t
HZWE
DATA VALID
t
PWE
t
HA
t
HD
t
LZWE
Truth Table
CE
H
L
L
L
WE
X
H
L
H
OE
X
L
X
H
High Z
Data out
Data in
High Z
I/O
Read
Write
Selected, outputs disabled
Mode
Deselect/power-down
Power
Standby (I
SB
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Notes
25. Data I/O is high impedance if OE = V
IH
.
26. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
27. During this period, the I/Os are in output state and input signals must not be applied.
28. Chip enable (CE) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Document #: 38-05442 Rev. *H
Page 8 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
