CY62256V
Switching Waveforms
(continued)
Write Cycle No. 2 (CE Controlled)
[10, 15, 16]
t
WC
ADDRESS
CE
t
SA
t
AW
WE
t
SD
DATA I/O
DATA
IN
VALID
t
HD
t
HA
t
SCE
Write Cycle No. 3 (WE Controlled, OE LOW)
[11, 16]
t
WC
ADDRESS
CE
t
AW
t
SA
WE
t
SD
DATA I/O
NOTE 17
t
HZWE
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
IH
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
t
HA
t
HD
DATA
IN
VALID
t
LZWE
Document #: 38-05057 Rev. *D
Page 8 of 13
CYPRESS [ CYPRESS SEMICONDUCTOR ]
