CY62256
Switching Waveforms
(continued)
Read Cycle No. 2
[13, 14]
CE
t
ACE
OE
t
DOE
DATA OUT
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
DATA VALID
t
PD
ICC
50%
ISB
t
HZOE
t
HZCE
t
RC
HIGH
IMPEDANCE
Write Cycle No. 1 (WE Controlled)
ADDRESS
[10, 15, 16]
t
WC
CE
t
AW
WE
t
SA
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE
17
t
HZOE
[10, 15, 16]
t
HD
DATA
IN
VALID
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
t
WC
t
SCE
t
SA
t
AW
t
HA
WE
t
SD
DATA I/O
DATA VALID
IN
t
HD
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
IH
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05248 Rev. *C
Page 6 of 12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
