CY7C024-55AC 参数 Datasheet PDF下载

CY7C024/0241

CY7C025/0251

Switching Waveforms

(continued)

Busy Timing Diagram No.1 (CE Arbitration)

CE

L

Valid First:

ADDRESS

L,R

CE

L

t

PS

CE

R

t

BLC

BUSY

R

7C024–23

ADDRESS MATCH

t

BHC

CE

R

Valid First:

ADDRESS

L,R

CE

R

t

PS

CE

L

t

BLC

BUSY

L

7C024–24

ADDRESS MATCH

t

BHC

Busy Timing Diagram No.2 (Address Arbitration)

Left Address Valid First

t

RC

or t

WC

ADDRESS

L

ADDRESS MATCH

t

PS

ADDRESS

R

t

BLA

BUSY

R

7C024–25

ADDRESS MISMATCH

t

BHA

Right Address Valid First:

t

RC

or t

WC

ADDRESS

R

ADDRESS MATCH

t

PS

ADDRESS

L

t

BLA

BUSY

L

7C024–26

ADDRESS MISMATCH

t

BHA

Note:

38. If t

PS

is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

Document #: 38-06035 Rev. *B

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