CY7C024/0241
CY7C025/0251
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
11/12L
I/O
0L
–I/O
15/17L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/S
V
CC
GND
CE
R
R/W
R
OE
R
A
0R
–A
11/12R
I/O
0R
–I/O
15/17R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Bus Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
Description
Selection Guide
7C024/0241–15
7C025/0251–15
Maximum Access Time (ns)
Typical Operating Current (mA)
Typical Standby Current for I
SB1
(mA)
15
190
50
7C024/0241–25
7C025/0251–25
25
170
40
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
ACE
after CE or t
DOE
after
OE is asserted. If the user of the CY7C024/0241 or
CY7C025/0251 wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024/0241, 1FFF for the CY7C025/0251) is the mailbox
for the right port and the second-highest memory location
(FFE for the CY7C024/0241, 1FFE for the CY7C025/0251) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The
interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the BUSY signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active BUSY to a port prevents that port from reading
its own mailbox and thus resetting the interrupt to it.
If your application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in
7C024/0241–35
7C025/0251–35
35
160
30
7C024/0241–55
7C025/0251–55
55
150
20
Architecture
The CY7C024/0241 and CY7C025/0251 consist of an array of
4K words of 16/18 bits each and 8K words of 16/18 bits each
of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S
pin, the CY7C024/0241 and CY7C025/0251 can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The CY7C024/0241 and CY7C025/0251 have an
automatic power-down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
DDD
after the data is presented on the other port.
Document #: 38-06035 Rev. *C
Page 4 of 21
CYPRESS [ CYPRESS SEMICONDUCTOR ]
