CY7C024/0241
CY7C025/0251
Logic Block Diagram
L
L
R/W
R
UB
R
L
LB
R
CE
R
OE
R
OE
L
I/O
8L
– I/O
15L
I/O
0L
– I/O
7L
I/O
CONTROL
I/O
CONTROL
I/O
8R
– I/O
15R
I/O
0R
– I/O
7R
BUSY
R
A
12R
(CY7C025/0251)
BUSY
L
(CY7C025/0251)
A
12L
A
11L
A
0L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
11R
A
0R
CE
L
OE
L
UB
L
LB
L
R/W
L
SEM
L
INT
L
INTERRUPT
SEMAPHORE
ARBITRATION
CE
R
OE
R
UB
R
LB
R
R/W
R
SEM
R
M/S
INT
R
Pin Configurations
84-Pin PLCC
Top View
SEM
L
CE
L
UB
L
LB
L
NC
A
11L
GND
I/O
1L
I/O
0L
OE
L
V
CC
R/W
L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
A
10L
A
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
9L
11 10 9 8 7 6 5 4 3 2
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
58
28
57
29
56
30
55
31
54
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
SEM
R
CE
R
UB
R
LB
R
NC
A
GND
I/O
15R
I/O
9R
OE
R
R/W
R
I/O
13R
I/O
14R
I/O
10R
I/O
11R
I/O
12R
GND
A
10R
A
9R
A
8R
A
7R
1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
CY7C024/5
65
64
63
62
61
60
59
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. I/O
0
–I/O
8
on the CY7C0241/0251.
3. I/O
9
–I/O
17
on the CY7C0241/0251.
4. A
12L
on the CY7C025/0251.
5. A
12R
on the CY7C025/0251.
Document #: 38-06035 Rev. *C
Page 2 of 21
CYPRESS [ CYPRESS SEMICONDUCTOR ]
